Intel Agilex Configuration User Manual page 82

Options
Allow user to control • On
FLASH_NRESET pin
• Off
Table 20. PFL II Flash Programming Parameters
Options
Flash programming IP • Area
optimization target
• Speed
Flash programming IP • 16
FIFO size
• 32
Add Block-CRC • On
verification
• Off
acceleration support
Table 21. PFL II FPGA Configuration Parameters
Options
What is the external Provide the frequency of your external clock.
clock frequency?
What is the flash Provide the access time from the flash data sheet.
access time?
Intel ® Agilex ™ Configuration User Guide
82
Value
Select the flash data width that is equivalent to the sum of the data width of two flash
memories. For example, if you are targeting dual solution, you must select 32 bits
because each CFI flash data width is 16 bits.
Creates a
memory device. A low signal resets the flash memory device. In burst mode, this pin is
available by default.
When using a Cypress GL flash memory, connect this pin to the
memory.
Value
Specifies the flash programming IP optimization. If you optimize the PFL II IP core for
Speed, the flash programming time is shorter, but the IP core uses more LEs. If you
optimize the PFL II IP core for Area, the IP core uses fewer LEs, but the flash
programming time is longer.
Specifies the FIFO size if you select Speed for flash programming IP optimization. The PFL
II IP core uses additional LEs to implement FIFO as temporary storage for programming
data during flash programming. With a larger FIFO size, programming time is shorter.
Adds a block to accelerate verification.
Value
Specifies the user-supplied clock frequency for the IP core to configure the FPGA. The
clock frequency must not exceed two times the maximum clock (
the FPGA can use for configuration. The PFL II IP core can divide the frequency of the
input clock maximum by two.
Specifies the flash access time. This information is available from the flash datasheet.
Intel recommends specifying a flash access time that is equal to or greater than the
required time.
For CFI parallel flash, the unit is in ns. For NAND flash, the unit is in μs. NAND flash uses
pages instead of bytes and requires greater access time. This option is disabled for quad
SPI flash.
Description
pin in the PFL II IP core to connect to the reset pin of the flash
FLASH_NRESET
Description
Description
3. Intel Agilex Configuration Schemes
UG-20205 | 2019.10.09
pin of the flash
RESET
) frequency
AVST_CLK
continued...
Send Feedback