Intel Agilex Configuration User Manual page 64

The total number of pages and the size of each page depends on the flash density. Here are some guidelines for storing your
designs to pages:
• Always store designs for different FPGA chains on different pages.
• You may choose store different designs for a FPGA chain on a single page or on multiple pages.
• When you choose to store the designs for a FPGA chain on a single page, the design order must match the JTAG chain
device order.
Use the generated
to conversion:
.pof
• Block mode—allows you to specify the start and end addresses for the page.
• Start mode—allows you to specify only the start address. The start address for each page must be on an 8 KB boundary.
If the first valid start address is
• Auto mode—allows the Intel Quartus Prime software to automatically determine the start address of the page. The Intel
Quartus Prime software aligns the pages on a 128 KB boundary. If the first valid start address is
start address is an multiple of
3.1.10.1.5. Storing Option Bits
In addition to design data, the flash memory stores the option bits. You must specify the address for the options bits in two
places: the PFL II IP and in the option bits address of the flash memory device.
The option bits contain the following information:
• The start address for each page.
•
The . version for flash programming. This value is the same for all pages.
pof
•
The
Page-Valid
after successfully programming the page.
You use the Programming File Generator dialog box to specify the Start address of the option bits. Specify your flash
device using Add Device on the Configuration Tab of the Programming File Generator dialog box. Then click OPTIONS
and EDIT to specify the Start address for the option bits. This Start address must match the address you specify for What
is the byte address of the option bits, in hex? when specifying the PFL II IP parameters.
Intel ® Agilex ™ Configuration User Guide
64
to create a flash memory device
.sof
, the next valid start address is an increment of
0×000000
.
0x20000
bits for each page. The
Page-Valid
. The following address modes are available for the
.pof
bit is bit 0 of the start address. The PLF II IP core writes this bit
3. Intel Agilex Configuration Schemes
UG-20205 | 2019.10.09
.sof
.
0×2000
, the next valid
0x000000
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