Intel Agilex Configuration User Manual page 71

3. Intel Agilex Configuration Schemes
UG-20205 | 2019.10.09
Figure 29. Page Start Address, End Address, and Page-Valid Bit Stored as Option Bits
The Page-Valid bits indicate whether each page is successfully programmed. The PFL II IP core sets the Page-Valid bits after successfully programming the pages.
Table 15. Byte Address Range for CFI Flash Memory Devices with Different Densities
CFI Device (Megabit)
8
16
32
64
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0x002000
(For flash byte addressing mode)
0x002001 Page Start Address [17:13]
0x002002
0x002003
0x002004
0x002005
0x002006
0x002007
Bit 7...Bit 1 Bit 0
Reserved Page Valid
Bit 7...Bit 3 Bit 2...Bit 0
Reserved
Bit 7...Bit 0
Page Start Address [25:18]
Bit 7...Bit 0
Page Start Address [33:26]
Bit 7...Bit 0
Page End Address [9:2]
Bit 7...Bit 0
Page End Address [17:10]
Bit 7...Bit 0
Page End Address [25:18]
Bit 7...Bit 0
Page End Address [33:26]
Address Range
–
0x0000000 0x00FFFFF
–
0x0000000 0x01FFFFF
–
0x0000000 0x03FFFFF
–
0x0000000 0x07FFFFF
Intel
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