Intel Agilex Configuration User Manual page 98

Figure 41. Connections for Programming the Serial Flash Devices using the JTAG Interface
Intel recommends using the JTAG interface to prepare the Quad SPI flash device for later use in AS mode.
Intel ® Agilex ™ Configuration User Guide
98
V
CCIO_SDM
AS x4 Flash Device
10 kΩ
10 kΩ
DATA0
DATA1
DATA2
DATA3
DCLK
V
CCIO_SDM
nCS
4.7 kΩ
GND
Resistor values can vary between 1
Perform signal integrity analysis to select
CONF_DONE connection
the resistor value for your setup.
to external host for
monitoring is optional.
V
CCIO_SDM
Intel FPGA
nSTATUS
nCONFIG
CONF_DONE
AS_DATA[0]
TCK
TDO
AS_DATA[1]
TMS
AS_DATA[2]
AS_DATA[3] TDI
AS_CLK
OSC_CLK_1
4.7 kΩ
External clock source to feed
MSEL [0]/AS_nCSO[0]
the is optional.
MSEL [1]
For external ref clk, OSC_CLK_1
MSEL [2]
is required.
AS fast mode: Pull MSEL [1] low using 4.7
AS normal mode: Pull MSEL [1] high using
3. Intel Agilex Configuration Schemes
UG-20205 | 2019.10.09
kΩ to 10 kΩ.
Download Cable
10-Pin Male Header
(JTAG Mode) (Top View)
3M Part number : 2510-6002UB
Pin 1
V
CCIO_SDM
1 kΩ
GND
kΩ resistor
4.7 kΩ resistor
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