Guidelines For Jtag Bst - Intel MAX 10 JTAG User Manual

UG-M10JTAG | 2019.05.10
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6. Guidelines for JTAG BST

Consider the following guidelines when you perform BST with the device:
•
If the "10..." pattern does not shift out of the instruction register through the
pin during the first clock cycle of the
reach the proper state. To solve this problem, try one of the following procedures:
— Verify that the TAP controller has reached the
advance the TAP controller to the
RESET
— Check the connections to the
pins on the device.
•
Perform a
ensure that known data is present at the device pins when you enter
mode. If the
is driven out. The state must be known and correct to avoid contention with other
devices in the system.
•
To perform testing before configuration, hold the
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state and send the
01100
test cycle before the first
SAMPLE/PRELOAD
update register contains 0, the data in the
OEJ
state, the TAP controller did not
SHIFT_IR
SHIFT_IR
state, return TAP controller to the
SHIFT_IR
code to the pin.
TMS
, , , and dedicated configuration
VCC GND JTAG
EXTEST
nCONGFIG
TDO
state correctly. To
test cycle to
EXTEST
update register
OUTJ
pin low.
ISO
9001:2015
Registered