Functional Description; Figure 1-2. Slm-5650B Block Diagram - Comtech EF Data SLM-5650B Installation And Operation Manual

1.2

Functional Description

SCT (1.8V)
RXC (1.8V)
RXC (LVDS)
25MHz
Unit Alarms
TX Alarms
RX Alarms
LCMX02
FPGA / CPLD
UART TX (3.3V I/O)
UART RX
Front Panel
Connector
Figure 1-2 depicts the functional block diagram for the SLM-5650B. The modem has been
designed to accommodate a wide range of currently required features, and to support both near-
and far-term advances in software-defined radio technology as well as advances in FEC
technology. It is designed for installation in fixed or mobile Earth Terminal (ET) facilities (sites)
using Defense Satellite Communications System III (DSCS III), DSCS III/Satellite Life
Enhancement Program (SLEP), Wideband Global Satcom (WGS), and commercial satellites.
The user has the ability to:
•
Add or change modular data interfaces
•
Utilize an extensive array of built-in test capabilities
•
Easily upgrade the modem's operational capabilities in the field
•
Easily update the modem's firmware in the field
•
Use a wide range of flexible remote control options
As shown in Figure 1-2, the modem accepts signals from a selected digital signal source and
modulates either a 70/140 MHz or L-Band Intermediate Frequency (IF) carrier with these signals.
The demodulator receives the Rx signal from either the 70/140 MHz or L-Band IF input interface,
then demodulates the IF carrier. Clock and data are recovered and output on a selected data
interface.
The Tx and Rx functions are independent with respect to coding, interleaving, overhead, and
scrambling. The modem does not allow simplex operation in the 70/140 and the L-Band IF
interfaces at the same time. The modem allows duplex operation in either one of the two IF
interfaces.
Introduction
SCT DAC
EIA Pri TX (1.8V)
EIA OH TX (1.8V)
HSSI Pri TX (LVDS)
IP TX (RGMII) Altera 10AX066H2F34
SCT (LVDS & 1.8V)
M&C – TX FPGA Lanes (1.8V)
M&C Config (1.8V)
25MHz
FIPS TX (LVDS)
IP Traffic (SerDes)
TRANSEC
192MHz
(3.3V I/O) (LVDS)
FIPS RX (LVDS)
RXC (LVDS & 1.8V)
EIA Pri RX (1.8V)
EIA OH RX (1.8V)
Altera 10AX066H2F34
HSSI Pri RX (LVDS)
IP RX (RGMII)
M&C – RX FPGA Lanes (1.8V)
M&C Config (1.8V)
25MHz
RX Clock
DAC
Marvell
Ethernet
IP Traffic (RMII)
Switch
M&C Config (MDIO)
(88E6321)
IP Traffic (SerDes)
M&C – TX FPGA
M&C Config (3.3V)
Lanes (1.8V)
3V
M&C – RX FPGA
Lanes (1.8V)
M&C 32.768kHz
M&C
MVF51NN151
M&C Config (3.3V) (3.3V I/O)
24MHz
SD Card
MRAM DDR 3
Adapter

Figure 1-2. SLM-5650B Block Diagram

DDR4
1.8V SPI
TX FPGA
TX I & Q Samples (LVDS)
(1.2V & 1.8V I/O)
Turbo TX
3.3 / 1.8V Level
Translator
Turbo Codec
(3.3V I/O)
3.3 / 1.8V Level
Translator
Turbo RX
M&C Config
RX FPGA
RX I & Q Samples (LVDS)
(1.2 & 1.8 I/O)
250MHz
Clock Distributor
DDR4
3.3 / 1.8V Level
3.3 / 1.8V Level Translator
Translator
192MHz (LVDS) 250MHz VCXO
10MHz Ref (3.3V)
Option Card
Connector
1–2
SLM-5650B Satellite Modem
Quad 16-bit
nanoDAC
(AD5685R)
AGC TX RF Output
1.8V SPI
2 Ch DAC
(DAC3482,
TX RF Front
900mW)
TX RF Output
Quad 16-bit
nanoDAC
(AD5685R)
AGC
1.8V SPI
1.8V SPI
2 Ch ADC
(LTC2157-14, RX RF Front
650mW)
PLL PLL
(1, 2, 5 or 10MHz)
20MHz
System Reference
-3.3V
MN-SLM-5650B
Revision 2
70/140MHz
L-Band
70/140MHz
RX RF Input
L-Band
RX RF Input
Reference Input
Power
+12V
Supply