Bdm Target To Host Serial Bit Timing (Logic 0) - Motorola HC12 Refrence Manual

Figure 8-4 shows the host receiving a logic zero from the target. Since the host is
asynchronous to the target, there is a 0- or 1-cycle delay from the host-generated fall-
ing edge on BKGD until the target perceives the bit. The host initiates the bit time, but
the target finishes it. To make certain the host receives a logic zero, the target drives
the BKGD pin low for 13 E-clock cycles, then briefly drives the signal high to speed up
the rising edge. The host samples the bit level about ten cycles after starting the bit
time.
ECLOCK
(TARGET
MCU)
HOST
DRIVE TO
BKGD PIN
TARGET MCU
DRIVE AND
SPEEDUP PULSE
PERCEIVED
START OF BIT TIME
BKGD PIN
Figure 8-4 BDM Target to Host Serial Bit Timing (Logic 0)
8.4.3 BDM Commands
All BDM opcodes are eight bits long, and can be followed by an address or data, as
indicated by the instruction.
Commands implemented in BDM control hardware are listed in
mands, except for BACKGROUND, do not require the CPU to be in BDM mode for ex-
ecution. The control logic uses CPU dead cycles to execute these instructions. If a
dead cycle cannot be found within 128 cycles, the control logic steals cycles from the
CPU.
CPU12
REFERENCE MANUAL
10 CYCLES
10 CYCLES
DEVELOPMENT AND DEBUG SUPPORT
HIGH-IMPEDANCE
SPEEDUP PULSE
HOST SAMPLES
BKGD PIN
Table 8-2. These com-
EARLIEST
START OF
NEXT BIT
CPU12 BDM TH0TIM
MOTOROLA
8-9