Table of Contents
Advertisement
Notice that parameters are at positive offsets from the frame pointer while locals are
at negative offsets. In the M68HC11, the indexed addressing mode uses only positive
offsets, so the frame pointer always points to the lowest address of any parameter or
local. After the function subroutine finishes, calculations are required to restore the
stack pointer to the mid-frame position between the locals and the parameters before
returning to the calling program. The CPU12 only requires execution of TFR X,S to
deallocate the local storage and return.
The concept of a frame pointer is supported in the CPU12 through a combination of
improved indexed addressing, universal transfer/exchange, and the LEA instruction.
These instructions work together to achieve more efficient handling of frame pointers.
It is important to consider the complete instruction set as a complex system with subtle
interrelationships rather than simply examining individual instructions when trying to
improve an instruction set. Adding or removing a single instruction can have unexpect-
ed consequences.
C.3 Increment and Decrement Operators
In C, the notation + + i or i – – is often used to form loop counters. Within limited con-
straints, the CPU12 loop primitives can be used to speed up the loop count and branch
function.
The CPU12 includes a set of six basic loop control instructions which decrement, in-
crement, or test a loop count register, and then branch if it is either equal to zero or not
equal to zero. The loop count register can be A, B, D, X, Y, or SP. A or B could be used
if the loop count fits in an 8-bit char variable; the other choices are all 16-bit registers.
The relative offset for the loop branch is a 9-bit signed value, so these instructions can
be used with loops as long as 256 bytes.
In some cases, the pre- or post-increment operation can be combined with an indexed
instruction to eliminate the cost of the increment operation. This is typically done by
post-compile optimization because the indexed instruction that could absorb the incre-
ment/decrement operation may not be apparent at compile time.
C.4 Higher Math Functions
In the CPU12, subtle characteristics of higher math operations such as IDIVS and
EMUL are arranged so a compiler can handle inputs and outputs more efficiently.
The most apparent case is the IDIVS instruction, which divides two 16-bit signed num-
bers to produce a 16-bit result. While the same function can be accomplished with the
EDIVS instruction (a 32 by 16 divide), doing so is much less efficient because extra
steps are required to prepare inputs to the EDIVS, and because EDIVS uses the Y in-
dex register. EDIVS uses a 32-bit signed numerator and the C compiler would typically
want to use a 16-bit value (the size of an integer data type). The 16-bit C value would
need to be sign-extended into the upper 16-bits of the 32-bit EDIVS numerator before
the divide operation.
CPU12
REFERENCE MANUAL
HIGH-LEVEL LANGUAGE SUPPORT
MOTOROLA
C-3
Advertisement
Table of Contents
