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7.7.3 Interrupt and Unimplemented Opcode Trap Exception Processing
If an exception was not caused by a reset, a return address is calculated.
Cycles 2.1and 2.2 are both S cycles (a 16-bit word), but the cycles are not identical
because the CPU12 performs different return address calculations for each type of ex-
ception.
When an X- or I-related interrupt causes the exception, the return address points
to the next instruction that would have been executed had processing not been in-
terrupted.
When an exception is caused by an SWI opcode or by an unimplemented opcode
(see
7.5 Unimplemented Opcode
dress after the opcode.
Once calculated, the return address is pushed onto the stack.
Cycles 3.1 through 9.1 are identical to cycles 3.2 through 9.2 for the rest of the se-
quence, except for X mask bit manipulation performed in cycle 8.1.
Cycle 3.1/3.2 is the first of three program word fetches that refill the instruction queue.
Cycle 4.1/4.2 pushes Y onto the stack.
Cycle 5.1/5.2 pushes X onto the stack.
Cycle 6.1/6.2 is the second of three program word fetches that refill the instruction
queue. During this cycle, the contents of the A and B accumulators are concatenated
into a 16-bit word in the order B:A. This makes register order in the stack frame the
same as that of the M68HC11, M6801, and the M6800.
Cycle 7.1/7.2 pushes the 16-bit word containing B:A onto the stack.
Cycle 8.1/8.2 pushes the 8-bit CCR onto the stack, then updates the mask bits.
When an XIRQ interrupt causes an exception, both X and I are set, which inhibits
further interrupts during exception processing.
When any other interrupt causes an exception, the I bit is set, but the X bit is not
changed.
Cycle 9.1/9.2 is the third of three program word fetches that refill the instruction queue.
It is the last cycle of exception processing. After this cycle the CPU starts executing
the first cycle of the instruction at the head of the instruction queue.
MOTOROLA
7-8
Trap), the return address points to the next ad-
EXCEPTION PROCESSING
CPU12
REFERENCE MANUAL
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