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Cycle-by-cycle operation 6-5
DAA instruction 6-69
DATA mnemonic 1-3
Data types 2-5
DBEQ instruction 6-70, A-25
DBNE instruction 6-71, A-25
DEC instruction 6-72
DECA instruction 6-73
DECB instruction 6-74
Decrement instructions 5-4, 6-72 to 6-77
Defuzzification 9-6, 9-22 to 9-24, 9-26, 9-29
DES instruction 6-75
DEX instruction 6-76
DEY instruction 6-77
Direct addressing mode 3-3
Division instructions 5-7
16-bit fractional 6-91
16-bit integer 6-94 to 6-95
32-bit extended 6-78 to 6-79
Divsion instructions C-3
EDIV instruction 6-78
EDIVS instruction 6-79
Effective address 3-2, 3-5, 6-128 to 6-130
EMACS instruction 5-11, 6-80, 9-1, 9-29
EMAXD 6-81
EMAXD instruction 6-81
EMAXM instruction 6-82, 9-1
EMIND instruction 6-83, 9-1
EMINM instruction 6-84
EMUL instruction 6-85
EMULS instruction 6-86
Enabling maskable interrupts 2-4
EORA instruction 6-87
EORB instruction 6-88
ETBL instruction 5-12, 6-89, 9-1
Even bytes 2-5
Exceptions 4-3, 7-1
Interrupts 7-3
Maskable interrupts 7-1, 7-4 to 7-5
Non-maskable interrupts 7-1, 7-4
Priority 7-2
Processing flow 7-6
Resets 7-1 to 7-3
Software interrupts 5-18, 6-196, 7-1, 7-6
Unimplemented opcode trap 7-1 to 7-2, 7-5
Vectors 7-1, 7-6
Exchange instructions 5-2, 6-90, 6-215 to 6-216,
B-11, B-13
Postbyte encoding A-24
CPU12
REFERENCE MANUAL
D
E
Execution cycles 6-5
Conditional 16-bit read 6-7
Conditional 8-bit read 6-7
Conditional 8-bit write 6-7
Free 6-5
Optional 4-4 to 4-5, 6-6
Program word access 6-6
Read indirect pointer 6-5
Read indirect PPAGE value 6-5
Read PPAGE 6-5
Read 16-bit data 6-6
Read 8-bit data 6-6
Stack 16-bit data 6-6
Stack 8-bit data 6-6
Unstack 16-bit data 6-7
Unstack 8-bit data 6-6
Vector fetch 6-7
Write PPAGE 6-5
Write 16-bit data 6-6
Write 8-bit data 6-6
Execution time 6-5
EXG instruction 6-90
Expanded memory 3-12, 4-3, 10-1, B-16,
C-4 to C-5
Addressing modes 3-12, 10-4 to 10-6
Bank switching 3-12, 10-1, 10-3 to 10-6
Chip-select circuits 10-4
Instructions 3-12, 5-17, 6-52, 6-176, 10-2 to 10-3
Overlay windows 10-1, 10-3 to 10-6
Page registers 3-12, 10-1, 10-4 to 10-6
Registers 10-5 to 10-6
Subroutines 5-17, 10-2, C-4 to C-5
Extended addressing mode 3-3
Extended division 5-7
Extension byte 3-5
External interrupts 7-5
External queue reconstruction 8-1
External reset 7-3
Fast math B-9
FDIV instruction 6-91
Fractional division 5-7
Frame pointer C-2 to C-3
Free cycle 6-5
Fuzzy logic 9-1
Antecedants 9-5
Consequents 9-5
Custom programming 9-26
Defuzzification 5-9, 9-6, 9-22 to 9-24, 9-26, 9-29
Fuzzification 5-9, 9-3, 9-26
Inference kernel 5-9, 9-2, 9-7
Inputs 5-9, 9-30
F
MOTOROLA
I-3
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