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2.1.5 Condition Code Register
This register contains five status indicators, two interrupt masking bits, and a STOP
instruction control bit. It is named for the five status indicators.
The status bits reflect the results of CPU operation as it executes instructions. The five
flags are half carry (H), negative (N), zero (Z), overflow (V), and carry/borrow (C). The
half-carry flag is used only for BCD arithmetic operations. The N, Z, V, and C status
bits allow for branching based on the results of a previous operation.
In some architectures, only a few instructions affect condition codes, so that multiple
instructions must be executed in order to load and test a variable. Since most CPU12
instructions automatically update condition codes, it is rarely necessary to execute an
extra instruction for this purpose. The challenge in using the CPU12 lies in finding in-
structions that do not alter the condition codes. The most important of these instruc-
tions are pushes, pulls, transfers, and exchanges.
It is always a good idea to refer to an instruction set summary (see
STRUCTION
REFERENCE) to check which condition codes are affected by a partic-
ular instruction.
The following paragraphs describe normal uses of the condition codes. There are oth-
er, more specialized uses. For instance, the C status bit is used to enable weighted
fuzzy logic rule evaluation. Specialized usages are described in the relevant portions
of this manual and in
2.1.5.1 S Control Bit
Setting the S bit disables the STOP instruction. Execution of a STOP instruction caus-
es the on-chip oscillator to stop. This may be undesirable in some applications. If the
CPU encounters a STOP instruction while the S bit is set, it is treated like a no-oper-
ation (NOP) instruction, and continues to the next instruction.
2.1.5.2 X Mask Bit
The XIRQ input is an updated version of the NMI input found on earlier generations of
MCUs. Non-maskable interrupts are typically used to deal with major system failures,
such as loss of power. However, enabling non-maskable interrupts before a system is
fully powered and initialized can lead to spurious interrupts. The X bit provides a mech-
anism for enabling non-maskable interrupts after a system is stable.
By default, the X bit is set to one during reset. As long as the X bit remains set, interrupt
service requests made via the XIRQ pin are not recognized. An instruction must clear
the X bit to enable non-maskable interrupt service requests made via the XIRQ pin.
Once the X bit has been cleared to zero, software cannot reset it to one by writing to
the CCR. The X bit is not affected by maskable interrupts.
When an XIRQ interrupt occurs after non-maskable interrupts are enabled, both the X
bit and the I bit are automatically set to prevent other interrupts from being recognized
during the interrupt service routine. The mask bits are set after the registers are
stacked, but before the interrupt vector is fetched.
CPU12
REFERENCE MANUAL
SECTION 6 INSTRUCTION
OVERVIEW
APPENDIX A IN-
GLOSSARY.
MOTOROLA
2-3
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