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After the firmware is enabled, BDM can be activated by the hardware BACKGROUND
command, by breakpoints tagged via the LIM breakpoint logic or the BDM tagging
mechanism, and by the BGND instruction. An attempt to activate BDM before firmware
has been enabled causes the MCU to resume normal instruction execution after a
brief delay.
BDM becomes active at the next instruction boundary following execution of the BDM
BACKGROUND command. Breakpoints can be configured to activate BDM before a
tagged instruction is executed.
While BDM is active, BDM control registers are mapped to addresses $FF00 to $FF06.
These registers are only accessible through BDM firmware or BDM hardware com-
mands.
8.4.4 BDM Registers
Some M68HC12 on-chip peripherals have a BDM control bit, which determines wheth-
er the peripheral function is available during BDM. If no bit is shown, the peripheral is
active in BDM.
8.4.2 BDM Serial Interface
The BDM serial interface uses a clocking scheme in which the external host generates
a falling edge on the BKGD pin to indicate the start of each bit time. This falling edge
must be sent for every bit, whether data is transmitted or received.
BKGD is an open drain pin that can be driven either by the MCU or by an external host.
Data is transferred MSB first, at 16 E-clock cycles per bit. The interface times out if 512
E-clock cycles occur between falling edges from the host. The hardware clears the
command register when a time-out occurs.
The BKGD pin is used to send and receive data. The following diagrams show timing
for each of these cases. Interface timing is synchronous to MCU clocks, but the exter-
nal host is asynchronous to the target MCU. The internal clock signal is shown for ref-
erence in counting cycles.
Figure 8-2
shows an external host transmitting a data bit to the BKGD pin of a target
M68HC12 MCU. The host is asynchronous to the target, so there is a 0- to 1-cycle de-
lay from the host-generated falling edge to the time when the target perceives the bit.
Ten target E-cycles later, the target senses the bit level on the BKGD pin. The host
can drive high during host-to-target transmission to speed up rising edges, because
the target does not drive the pin during this time.
CPU12
REFERENCE MANUAL
describes the registers.
DEVELOPMENT AND DEBUG SUPPORT
MOTOROLA
8-7
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