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3.7 Relative Addressing Mode
The relative addressing mode is used only by branch instructions. Short and long con-
ditional branch instructions use relative addressing mode exclusively, but branching
versions of bit manipulation instructions (BRSET and BRCLR) use multiple addressing
modes, including relative mode. Refer to
more information.
Short branch instructions consist of an 8-bit opcode and a signed 8-bit offset contained
in the byte that follows the opcode. Long branch instructions consist of an 8-bit pre-
byte, an 8-bit opcode and a signed 16-bit offset contained in the two bytes that follow
the opcode.
Each conditional branch instruction tests certain status bits in the condition code reg-
ister. If the bits are in a specified state, the offset is added to the address of the next
memory location after the offset to form an effective address, and execution continues
at that address; if the bits are not in the specified state, execution continues with the
instruction immediately following the branch instruction.
Bit-condition branches test whether bits in a memory byte are in a specific state. Var-
ious addressing modes can be used to access the memory location. An 8-bit mask op-
erand is used to test the bits. If each bit in memory that corresponds to a one in the
mask is either set (BRSET) or clear (BRCLR), an 8-bit offset is added to the address
of the next memory location after the offset to form an effective address, and execution
continues at that address; if all the bits in memory that correspond to a one in the mask
are not in the specified state, execution continues with the instruction immediately fol-
lowing the branch instruction.
Both 8-bit and 16-bit offsets are signed two's complement numbers to support branch-
ing upward and downward in memory. The numeric range of short branch offset val-
ues is $80 (–128) to $7F (127). The numeric range of long branch offset values is
$8000 (–32768) to $7FFF (32767). If the offset is zero, the CPU executes the instruc-
tion immediately following the branch instruction, regardless of the test involved.
Since the offset is at the end of a branch instruction, using a negative offset value can
cause the PC to point to the opcode and initiate a loop. For instance, a branch always
(BRA) instruction consists of two bytes, so using an offset of $FE sets up an infinite
loop; the same is true of a long branch always (LBRA) instruction with an offset of
$FFFC.
An offset that points to the opcode can cause a bit-condition branch to repeat execu-
tion until the specified bit condition is satisfied. Since bit condition branches can con-
sist of four, five, or six bytes depending on the addressing mode used to access the
byte in memory, the offset value that sets up a loop can vary. For instance, using an
offset of $FC with a BRCLR that accesses memory using an 8-bit indexed postbyte
sets up a loop that executes until all the bits in the specified memory byte that corre-
spond to ones in the mask byte are cleared.
MOTOROLA
3-4
3.9 Instructions Using Multiple Modes
ADDRESSING MODES
for
CPU12
REFERENCE MANUAL
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