Motorola HC12 Refrence Manual page 320

After REVW finishes, A will hold the truth value (weighted) for the last rule in the rule
list. The V condition code bit should be one because the last element before the $FFFF
end marker should have been a rule consequent. If V is zero after executing REVW,
it indicates the rule list was structured incorrectly.
9.5.2.2 Interrupt Details
The REVW instruction includes a three-cycle processing loop for each word in the rule
list (this loop expands to five cycles between antecedents and consequents to allow
time for the multiplication with the rule weight). Within this loop, a check is performed
to see if any qualified interrupt request is pending. If an interrupt is detected, the cur-
rent CPU registers are stacked and the interrupt is honored. When the interrupt ser-
vice routine finishes, an RTI instruction causes the CPU to recover its previous context
from the stack, and the REVW instruction is resumed as if it had not been interrupted.
The stacked value of the program counter (PC), in case of an interrupted REVW in-
struction, points to the REVW instruction rather than the instruction that follows. This
causes the CPU to try to execute a new REVW instruction upon return from the inter-
rupt. Since the CPU registers (including the C bit and V bit in the condition codes reg-
ister) indicate the current status of the interrupted REVW instruction, this effectively
causes the rule evaluation operation to resume from where it left off.
9.5.2.3 Cycle-by-Cycle Details for REVW
The central element of the REVW instruction is a three-cycle loop that is executed
once for each word in the rule list. For the special case pass (where the $FFFE sepa-
rator word is read between the rule antecedents and the rule consequents, and
weights enabled by the C bit equal one), this loop takes five cycles. There is a small
amount of housekeeping activity to get this loop started as REVW begins and a small
sequence to end the instruction. If an interrupt comes, there is a special small se-
quence to save CPU status on the stack before the interrupt is serviced.
Figure 9-10 is a detailed flow diagram for the REVW instruction. Each rectangular box
represents one CPU clock cycle. Decision blocks and connecting arrows are consid-
ered to take no time at all. The letters in the small rectangles in the upper left corner
of each bold box correspond to the execution cycle codes (refer to
STRUCTION GLOSSARY
or no data is transferred. Upper case letters indicate cycles where 16-bit data could be
transferred.
MOTOROLA
9-20
for details). Lower case letters indicate a cycle where 8-bit
FUZZY LOGIC SUPPORT
SECTION 6 IN-
CPU12
REFERENCE MANUAL