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4.3.3 Branches
Branch instructions cause execution flow to change when specific pre-conditions exist.
The CPU12 instruction set includes short conditional branches, long conditional
branches, and bit-condition branches. Types and conditions of branch instructions are
described in
5.18 Branch
larly, but there are differences in overall cycle counts between the various types. Loop
primitive instructions are a special type of branch instruction used to implement
counter-based loops.
Branch instructions have two execution cases. Either the branch condition is satisfied,
and a change of flow takes place, or the condition is not satisfied, and no change of
flow occurs.
4.3.3.1 Short Branches
The "not-taken" case for short branches is simple. Since the instruction consists of a
single word containing both an opcode and an 8-bit offset, the queue advances, an-
other program word is fetched, and execution continues with the next instruction.
The "taken" case for short branches requires that the queue be refilled so that execu-
tion can continue at a new address. First, the effective address of the destination is
calculated using the relative offset in the instruction. Then, the address is loaded into
the program counter, and the CPU performs three program word fetches at the new
address. The first two words fetched are loaded into the instruction queue during the
second and third cycles of the sequence. The third fetch cycle is performed in antici-
pation of a queue advance, which may occur during the first cycle of the next instruc-
tion. If the queue is not yet ready to advance at that time, the third word of program
information is held in the buffer.
4.3.3.2 Long Branches
The "not-taken" case for all long branches requires three cycles, while the "taken" case
requires four cycles. This is due to differences in the amount of program information
needed to fill the queue.
Long branch instructions begin with a $18 prebyte which indicates that the opcode is
on page 2 of the opcode map. The CPU12 treats the prebyte as a special one-byte
instruction. If the prebyte is not aligned, the first cycle is used to perform a program
word access; if the prebyte is aligned, the first cycle is used to perform a free cycle.
The first cycle for the prebyte is executed whether or not the branch is taken.
The first cycle of the branch instruction is an optional cycle. Optional cycles make the
effects of byte-sized and misaligned instructions consistent with those of aligned word-
length instructions. Optional cycles are always performed, but serve different purpos-
es determined by instruction alignment. Program information is always fetched as
aligned 16-bit words. When an instruction consists of an odd number of bytes, and the
first byte is aligned with an even byte boundary, an optional cycle is used to make an
additional program word access that maintains queue order. In all other cases, the op-
tional cycle appears as a free cycle.
MOTOROLA
4-4
Instructions. All branch instructions affect the queue simi-
INSTRUCTION QUEUE
CPU12
REFERENCE MANUAL
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