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This section discusses expansion memory principles that apply to the entire M68HC12
family. Some family devices do not have memory expansion capabilities, and the size
of the expanded memory can also vary. Please refer to the documentation for a deriv-
ative to determine details of implementation.
10.1 Expansion System Description
Certain members of the M68HC12 family incorporate hardware that supports address-
ing a larger memory space than the standard 64 Kbytes. The expanded memory sys-
tem uses fast on-chip logic to implement a transparent paged memory or bank-
switching scheme.
Increased code efficiency is the greatest advantage of using bank switching instead of
implementing a large linear address space. In systems with large linear address spac-
es, instructions require more bits of information to address a memory location, and
CPU overhead is greater. Other advantages of bank switching include the ability to
change the size of system memory, and the ability to use various types of external
memory.
However, the add-on bank switching schemes used in other microcontrollers have
known weaknesses. These include the cost of external glue logic, increased program-
ming overhead to change banks, and the need to disable interrupts while banks are
switched.
The M68HC12 system requires no external glue logic. Bank switching overhead is re-
duced by implementing control logic in the MCU. Interrupts do not need to be disabled
during switching because switching tasks are incorporated in special instructions that
greatly simplify program access to extended memory. Operation of the bank-switching
logic is transparent to the CPU.
The CPU12 has a linear 64-Kbyte address space. All MCU system resources, includ-
ing control registers for on-chip peripherals and on-chip memory arrays, are mapped
into this space. In a typical M68HC12 derivative, the resources have default addresses
out of reset, but can be re-mapped to other addresses by means of control registers
in the on-chip integration module.
Memory expansion control logic is outside the CPU. A block of circuitry in the MCU
integration module manages overlays that occupy pre-defined locations in the 64-
Kbyte space addressed by the CPU. These overlays can be thought of as windows
through which the CPU accesses information in the expanded memory space.
There are three overlay windows. The program window expands program memory,
the data window is used for independent data expansion, and the extra window ex-
pands access to special types of memory such as EEPROM. The program window al-
ways occupies the 16-Kbyte space from $8000 to $BFFF. Data and extra windows can
vary in size and location.
CPU12
REFERENCE MANUAL
SECTION 10
MEMORY EXPANSION
MEMORY EXPANSION
MOTOROLA
10-1
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