Jump And Subroutine Instructions - Motorola HC12 Refrence Manual

5.20 Jump and Subroutine Instructions

Jump instructions cause immediate changes in sequence. The JMP instruction loads
the PC with an address in the 64-Kbyte memory map, and program execution contin-
ues at that address. The address can be provided as an absolute 16-bit address or
determined by various forms of indexed addressing.
Subroutine instructions optimize the process of transferring control to a code segment
that performs a particular task. A short branch (BSR), a jump (JSR), or an expanded-
memory call (CALL) can be used to initiate subroutines. There is no LBSR instruction,
but a PC-relative JSR performs the same function. A return address is stacked, then
execution begins at the subroutine address. Subroutines in the normal 64-Kbyte ad-
dress space are terminated with an RTS instruction. RTS unstacks the return address
so that execution resumes with the instruction after BSR or JSR.
The CALL instruction is intended for use with expanded memory. CALL stacks the val-
ue in the PPAGE register and the return address, then writes a new value to PPAGE
to select the memory page where the subroutine resides. The page value is an imme-
diate operand in all addressing modes except indexed indirect modes; in these modes,
an operand points to locations in memory where the new page value and subroutine
address are stored. The RTC instruction is used to terminate subroutines in expanded
memory. RTC unstacks the PPAGE value and the return address so that execution
resumes with the next instruction after CALL. For software compatibility, CALL and
RTC execute correctly on devices that do not have expanded addressing capability.
Table 5-21 summarizes the jump and subroutine instructions.
Table 5-21 Jump and Subroutine Instructions
Mnemonic
BSR
CALL Call Subroutine in Expanded Memory
JMP
JSR
RTC
RTS
CPU12
REFERENCE MANUAL
Function
Branch to Subroutine
Jump
Jump to Subroutine
Return from Call
Return from Subroutine
INSTRUCTION SET OVERVIEW
Operation
⇒
SP – 2 SP
⇒
: RTN : M
RTN M
H L (SP)
⇒
Subroutine address
⇒
SP – 2 SP
⇒
:RTN : M
RTN M
H L (SP) (SP+1)
⇒
SP – 1 SP
⇒
(PPAGE) M
(SP)
⇒
Page PPAGE
⇒
Subroutine address
Subroutine Address ⇒ PC
⇒
SP – 2 SP
⇒
: RTN : M
RTN M
H L (SP)
⇒
Subroutine address
⇒
: M : PC
M PC
(SP) (SP+1) H
⇒
SP + 2
SP
⇒
M PPAGE
(SP)
⇒
SP + 1
SP
⇒
: M : PC
M PC
(SP) (SP+1) H
⇒
SP + 2
SP
MOTOROLA
(SP+1)
PC
PC
(SP+1)
PC
L
L
5-17