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WAI
(SP) – $0002 ⇒ SP; RTN
Operation:
(SP) – $0002 ⇒ SP; Y
(SP) – $0002 ⇒ SP; X
(SP) – $0002 ⇒ SP; B : A⇒ (M
(SP) – $0001 ⇒ SP; CCR ⇒ (M
Stop CPU Clocks
Description:
Puts the CPU into a wait state. Uses the address of the instruction fol-
lowing WAI as a return address. Stacks the return address, index regis-
ters Y and X, accumulators B and A, and the CCR, decrementing the SP
before each item is stacked.
The CPU then enters a wait state for an integer number of bus clock cy-
cles. During the wait state, CPU clocks are stopped, but other MCU
clocks can continue to run. The CPU leaves the wait state when it sens-
es an interrupt that has not been masked.
Upon leaving the wait state, the CPU sets the appropriate interrupt mask
bit(s), fetches the vector corresponding to the interrupt sensed, and in-
struction execution continues at the location the vector points to.
Condition Codes and Boolean Formulas:
S
–
Although the WAI instruction itself does not alter the condition codes,
the interrupt that causes the CPU to resume processing also causes
the I mask bit (and the X mask bit, if the interrupt was XIRQ) to be set
as the interrupt vector is fetched.
Addressing Modes, Machine Code, and Execution Times:
Source Form
WAI (before interrupt)
(when interrupt comes)
CPU12
REFERENCE MANUAL
Wait for Interrupt
: Y
H
: X
H
X
H
I
N
Z
–
–
–
–
–
Address Mode
INH
3E
INSTRUCTION GLOSSARY
⇒ (M
: RTN
: M
H
L
(SP)
⇒ (M
: M
(SP + 1)
L
(SP)
⇒ (M
: M
(SP + 1)
L
(SP)
: M
(SP + 1)
(SP)
)
(SP)
V
C
–
–
Object Code
WAI
(SP + 1)
)
)
)
)
Cycles
Access Detail
8
OSSSfSsf
5
VfPPP
MOTOROLA
6-213
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