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In the "not-taken" case, the queue must advance so that execution can continue with
the next instruction. Two cycles are used to refill the queue. Alignment determines how
the second of these cycles is used.
In the "taken" case, the effective address of the branch is calculated using the 16-bit
relative offset contained in the second word of the instruction. This address is loaded
into the program counter, then the CPU performs three program word fetches at the
new address. The first two words fetched are loaded into the instruction queue during
the second and third cycles of the sequence. The third fetch cycle is performed in an-
ticipation of a queue advance, which may occur during the first cycle of the next
instruction. If the queue is not yet ready to advance, the third word of program infor-
mation is held in the buffer.
4.3.3.3 Bit Condition Branches
Bit-conditional branch instructions read a location in memory, and branch if the bits in
that location are in a certain state. These instructions can use direct, extended, or in-
dexed addressing modes. Indexed operations require varying amounts of information
to determine the effective address, so instruction length varies according to the mode
used, which in turn affects the amount of program information fetched. In order to
shorten execution time, these branches perform one program word fetch in anticipa-
tion of the "taken" case. The data from this fetch is overwritten by subsequent fetches
in the "not-taken" case.
4.3.3.4 Loop Primitives
The loop primitive instructions test a counter value in a register or accumulator, and
branch to an address specified by a 9-bit relative offset contained in the instruction if
a specified pre-condition is met. There are auto-increment and auto-decrement ver-
sions of the instructions. The test and increment/decrement operations are performed
on internal CPU registers, and require no additional program information. In order to
shorten execution time, these branches perform one program word fetch in anticipa-
tion of the "taken" case. The data from this fetch is overwritten by subsequent fetches
in the "not-taken" case. The "taken" case performs two additional program word fetch-
es at the new address. In the "not-taken" case, the queue must advance so that exe-
cution can continue with the next instruction. Two cycles are used to refill the queue.
4.3.4 Jumps
JMP is the simplest change of flow instruction. JMP can use extended or indexed ad-
dressing. Indexed operations require varying amounts of information to determine the
effective address, so instruction length varies according to the mode used, which in
turn affects the amount of program information fetched. All forms of JMP perform three
program word fetches at the new address. The first two words fetched are loaded into
the instruction queue during the second and third cycles of the sequence. The third
fetch cycle is performed in anticipation of a queue advance, which may occur during
the first cycle of the next instruction. If the queue is not yet ready to advance, the third
word of program information is held in the buffer.
CPU12
REFERENCE MANUAL
INSTRUCTION QUEUE
MOTOROLA
4-5
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