Condition Code Changes; Object Code Notation - Motorola HC12 Refrence Manual

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Each entry contains symbolic and textual descriptions of operation, information con-
cerning the effect of operation on status bits in the condition code register, and a table
that describes assembler syntax, cycle count, and cycle-by-cycle execution of the in-
struction.

6.2 Condition Code Changes

The following special characters are used to describe the effects of instruction execu-
tion on the status bits in the condition codes register.
– — Status bit not affected by operation.
0 — Status bit cleared by operation.
1 — Status bit set by operation.
∆ — Status bit affected by operation.
⇓ — Status bit may be cleared or remain set, but is not set by operation.
⇑ — Status bit may be set or remain cleared, but is not cleared by operation.
? — Status bit may be changed by operation but the final state is not defined.
! — Status bit used for a special purpose.

6.3 Object Code Notation

The digits 0 to 9 and the upper case letters A to F are used to express hexadecimal
values. Pairs of lower case letters represent the 8-bit values as described below.
dd — 8-bit direct address $0000 to $00FF. (High byte assumed to be $00).
ee — High-order byte of a 16-bit constant offset for indexed addressing.
eb — Exchange/Transfer post-byte.
ff — Low-order eight bits of a 9-bit signed constant offset for indexed addressing, or
hh — High-order byte of a 16-bit extended address.
ii — 8-bit immediate data value.
jj — High-order byte of a 16-bit immediate data value.
kk — Low-order byte of a 16-bit immediate data value.
lb — Loop primitive (DBNE) post-byte.
ll — Low-order byte of a 16-bit extended address.
mm — 8-bit immediate mask value for bit manipulation instructions.
pg — Program overlay page (bank) number used in CALL instruction.
qq — High-order byte of a 16-bit relative offset for long branches.
tn — Trap number $30–$39 or $40–$FF.
rr — Signed relative offset $80 (–128) to $7F (+127).
xb — Indexed addressing post-byte.
MOTOROLA
6-2
low-order byte of a 16-bit constant offset for indexed addressing.
Set bits indicate bits to be affected.
Offset relative to the byte following the relative offset byte, or
low-order byte of a 16-bit relative offset for long branches.
INSTRUCTION GLOSSARY
CPU12
REFERENCE MANUAL

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