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BRCLR
Operation:
If (M)
Description:
Performs bitwise logical AND on memory location M and the mask sup-
plied with the instruction, then branches if and only if all bits with a value
of one in the mask byte correspond to bits with a value of zero in the test-
ed byte. Mask operands can be located at PC + 1, PC + 2, or PC + 4,
depending on addressing mode. The branch offset is referenced to the
next address after the relative offset (rr) which is the last byte of the in-
struction object code.
See
Condition Codes and Boolean Formulas:
S
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
BRCLR opr8a, msk8, rel8
BRCLR opr16a, msk8, rel8
BRCLR oprx0_xysp, msk8, rel8
BRCLR oprx9,xysp, msk8, rel8
BRCLR oprx16,xysp, msk8, rel8
Notes:
1. Indirect forms of indexed addressing cannot be used with this instruction.
CPU12
REFERENCE MANUAL
Branch if Bits Cleared
•
(Mask) = 0, then branch
3.7 Relative Addressing Mode
X
H
I
N
Z
–
–
–
–
–
Address Mode
DIR
EXT
IDX
IDX1
IDX2
INSTRUCTION GLOSSARY
for details of branch execution.
V
C
–
–
1
Object Code
4F dd mm rr
1F hh ll mm rr
0F xb mm rr
0F xb ff mm rr
0F xb ee ff mm
rr
BRCLR
Access
Cycles
Detail
4
rPPP
5
rfPPP
4
rPPP
6
rffPPP
8
frPffPPP
MOTOROLA
6-45
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