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CLI
⇒ I bit
0
Operation:
Description:
Clears the I mask bit. This instruction is assembled as ANDCC #$EF.
The ANDCC instruction can be used to clear any combination of bits in
the CCR in one operation.
When the I bit is cleared, interrupts are enabled. There is a one cycle
(bus clock) delay in the clearing mechanism for the I bit so that, if inter-
rupts were previously disabled, the next instruction after a CLI will
always be executed, even if there was an interrupt pending prior to exe-
cution of the CLI instruction.
Condition Codes and Boolean Formulas:
S
–
I:
Addressing Modes, Machine Code, and Execution Times:
Source Form
CLI translates to...
ANDCC #$EF
CPU12
REFERENCE MANUAL
Clear Interrupt Mask
X
H
I
N
Z
–
–
0
–
–
0; Cleared.
Address Mode
IMM
INSTRUCTION GLOSSARY
V
C
–
–
Object Code
10 EF
CLI
Cycles
Access Detail
1
P
MOTOROLA
6-55
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