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TRAP
(SP) – $0002 ⇒ SP; RTN
Operation:
(SP) – $0002 ⇒ SP; Y
(SP) – $0002 ⇒ SP; X
(SP) – $0002 ⇒ SP; B : A⇒ (M
(SP) – $0001 ⇒ SP; CCR ⇒ (M
1 ⇒ I
(Trap Vector) ⇒ PC
Description:
Traps unimplemented opcodes. There are opcodes in all 256 positions
in the page 1 opcode map, but only 54 of the 256 positions on page 2 of
the opcode map are used. If the CPU attempts to execute one of the un-
implemented opcodes on page 2, an opcode trap interrupt occurs. Un-
implemented opcode traps are essentially interrupts that share the
$FFF8:$FFF9 interrupt vector.
TRAP uses the next address after the unimplemented opcode as a re-
turn address. It stacks the return address, index registers Y and X, ac-
cumulators B and A, and the CCR, automatically decrementing the SP
before each item is stacked. The I mask bit is then set, the PC is loaded
with the trap vector, and instruction execution resumes at that location.
This instruction is not maskable by the I bit. Refer to
CEPTION PROCESSING
Condition Codes and Boolean Formulas:
S
–
I:
Addressing Modes, Machine Code, and Execution Times:
Source Form
TRAP trapnum
Notes:
1. The value tn represents an unimplemented page 2 opcode in either of the two ranges $30 to $39 or $40 to $FF.
CPU12
REFERENCE MANUAL
Unimplemented Opcode Trap
H
H
X
H
I
N
Z
–
–
1
–
–
1; Set.
Address Mode
INH
INSTRUCTION GLOSSARY
⇒ (M
: RTN
H
L
(SP)
⇒ (M
: Y
: M
(SP + 1)
L
(SP)
⇒ (M
: X
: M
(SP + 1)
L
(SP)
: M
(SP + 1)
(SP)
)
(SP)
for more information.
V
C
–
–
Object Code
1
$18 tn
TRAP
: M
(SP + 1)
)
)
)
)
SECTION 7 EX-
Cycles
Access Detail
11
OfVSPSSPSsP
MOTOROLA
6-205
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