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STOP
(SP) – $0002 ⇒ SP; RTN
Operation:
(SP) – $0002 ⇒ SP; Y
(SP) – $0002 ⇒ SP; X
(SP) – $0002 ⇒ SP; B : A⇒ (M
(SP) – $0001 ⇒ SP; CCR ⇒ (M
Stop All Clocks
Description:
When the S control bit is set, STOP is disabled and operates like a two-
cycle NOP instruction. When the S bit is cleared, STOP stacks CPU con-
text, stops all system clocks, and puts the device in standby mode.
Standby operation minimizes system power consumption. The contents
of registers and the states of I/O pins remain unchanged.
Asserting the RESET, XIRQ, or IRQ signals ends standby mode. Stack-
ing on entry to STOP allows the CPU to recover quickly when an inter-
rupt is used, provided a stable clock is applied to the device. If the
system uses a clock reference crystal that also stops during low-power
mode, crystal start-up delay lengthens recovery time.
If XIRQ is asserted while the X mask bit = 0 (XIRQ interrupts enabled),
execution resumes with a vector fetch for the XIRQ interrupt. If the X
mask bit = 1(XIRQ interrupts disabled), a two-cycle recovery sequence
including an O cycle is used to adjust the instruction queue, and execu-
tion continues with the next instruction after STOP.
Condition Codes and Boolean Formulas:
S
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
STOP (entering STOP)
(exiting STOP)
(continue)
(if STOP disabled)
CPU12
REFERENCE MANUAL
Stop Processing
: Y
H
: X
H
X
H
I
N
Z
–
–
–
–
–
Address Mode
INH
18 3E
INSTRUCTION GLOSSARY
⇒ (M
: RTN
: M
H
L
(SP)
⇒ (M
: M
(SP + 1)
L
(SP)
⇒ (M
: M
(SP + 1)
L
(SP)
: M
(SP + 1)
(SP)
)
(SP)
V
C
–
–
Object Code
STOP
(SP + 1)
)
)
)
)
Cycles
Access Detail
9
OOSSSfSsf
5
VfPPP
2
fO
2
OO
MOTOROLA
6-189
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