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IBEQ
(Counter) + 1 ⇒ Counter
Operation:
If (Counter) = 0, then (PC) + $0003 + Rel ⇒ PC,
Description:
Add one to the specified counter register A, B, D, X, Y, or SP. If the
counter register has reached zero, branch to the specified relative des-
tination. The IBEQ instruction is encoded into three bytes of machine
code including a 9-bit relative offset (–256 to +255 locations from the
start of the next instruction).
DBEQ and TBEQ instructions are similar to IBEQ except that the counter
is decremented or tested rather than being incremented. Bits 7 and 6 of
the instruction postbyte are used to determine which operation is to be
performed.
Condition Codes and Boolean Formulas:
S
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
IBEQ abdxys, rel9
Notes:
1. Encoding for lb is summarized in the following table. Bit 3 is not used (don't care), bit 5 selects branch on zero
(IBEQ – 0) or not zero (IBNE – 1) versions, and bit 0 is the sign bit of the 9-bit relative offset. Bits 7 and 6 should
be 1:0 for IBEQ.
Count
Bits 2:0
Register
A
B
D
X
Y
SP
MOTOROLA
6-92
Increment and Branch if Equal
X
H
I
N
Z
–
–
–
–
–
Address Mode
REL
Source Form
000
IBEQ A, rel9
001
IBEQ B, rel9
IBEQ D, rel9
100
101
IBEQ X, rel9
110
IBEQ Y, rel9
111
IBEQ SP, rel9
INSTRUCTION GLOSSARY
to Zero
V
C
–
–
1
Object Code
04 lb rr
Object Code
(if offset is positive)
04 80 rr
04 81 rr
04 84 rr
04 85 rr
04 86 rr
04 87 rr
IBEQ
Cycles
Access Detail
3/3
PPP
Object Code
(if offset is negative)
04 90 rr
04 91 rr
04 94 rr
04 95 rr
04 96 rr
04 97 rr
CPU12
REFERENCE MANUAL
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