Table of Contents
Advertisement
Operand size is also a potential problem in the extended multiply operations but the
difficulty can be minimized by putting the results in CPU registers. Having higher pre-
cision math instructions is not necessarily a requirement for supporting high-level lan-
guage because these functions can be performed as library functions. However, if an
application requires these functions, the code is much more efficient if the MCU can
use native instructions instead of relatively large, slow routines.
C.5 Conditional If Constructs
In the CPU12 instruction set, most arithmetic and data manipulation instructions auto-
matically update the condition code register, unlike other architectures that only
change condition codes during a few specific compare instructions. The CPU12 in-
cludes branch instructions that perform conditional branching based on the state of the
indicators in the condition codes register. Short branches use a single byte relative off-
set that allows branching to a destination within about ±128 locations from the branch.
Long branches use a 16-bit relative offset that allows conditional branching to any lo-
cation in the 64-Kbyte map.
C.6 Case and Switch Statements
Case and switch statements (and computed GOTOs) can use PC-relative indirect ad-
dressing to determine which path to take. Depending upon the situation, cases can
use either the constant offset variation or the accumulator D offset variation of indirect
indexed addressing.
C.7 Pointers
The CPU12 supports pointers by allowing direct arithmetic operations on the 16-bit in-
dex registers (LEAS, LEAX, and LEAY instructions) and by allowing indexed indirect
addressing modes.
C.8 Function Calls
Bank switching is a fairly common way of adapting a CPU with a 16-bit address bus to
accommodate more than 64-Kbytes of program memory space. One of the most sig-
nificant drawbacks of this technique has been the requirement to mask (disable) inter-
rupts while the bank page value was being changed. Another problem is that the
physical location of the bank page register can change from one MCU derivative to an-
other (or even due to a change to mapping controls by a user program). In these situ-
ations, an operating system program has to keep track of the physical location of the
page register. The CPU12 addresses both of these problems with the uninterruptible
CALL and return from call (RTC) instructions.
The CALL instruction is similar to a JSR instruction, except that the programmer sup-
plies a destination page value as part of the instruction. When CALL executes, the old
page value is saved on the stack and the new page value is written to the bank page
register. Since the CALL instruction is uninterruptible, this eliminates the need to sep-
arately mask off interrupts during the context switch.
MOTOROLA
C-4
HIGH-LEVEL LANGUAGE SUPPORT
CPU12
REFERENCE MANUAL
Advertisement
Table of Contents
