Table of Contents
Advertisement
7.4.1 Non-Maskable Interrupt Request (XIRQ)
The XIRQ input is an updated version of the NMI input of earlier MCUs. The XIRQ
function is disabled during system reset and upon entering the interrupt service routine
for an XIRQ interrupt.
During reset, both the I bit and the X bit in the CCR are set. This disables maskable
interrupts and interrupt service requests made by asserting the XIRQ signal. After min-
imum system initialization, software can clear the X bit using an instruction such as
ANDCC #$BF. Software cannot reset the X bit from zero to one once it has been
cleared, and interrupt requests made via the XIRQ pin become non-maskable. When
a non-maskable interrupt is recognized, both the X and I bits are set after context is
saved. The X bit is not affected by maskable interrupts. Execution of an RTI at the end
of the interrupt service routine normally restores the X and I bits to the pre-interrupt
request state.
7.4.2 Maskable Interrupts
Maskable interrupt sources include on-chip peripheral systems and external interrupt
service requests. Interrupts from these sources are recognized when the global inter-
rupt mask bit (I) in the CCR is cleared. The default state of the I bit out of reset is one,
but it can be written at any time.
The integration module manages maskable interrupt priorities. Typically, an on-chip
interrupt source is subject to masking by associated bits in control registers in addition
to global masking by the I bit in the CCR. Sources generally must be enabled by writing
one or more bits in associated control registers. There may be other interrupt-related
control bits and flags, and there may be specific register read-write sequences asso-
ciated with interrupt service. Refer to individual on-chip peripheral descriptions for de-
tails.
7.4.3 Interrupt Recognition
Once enabled, an interrupt request can be recognized at any time after the I mask bit
is cleared. When an interrupt service request is recognized, the CPU responds at the
completion of the instruction being executed. Interrupt latency varies according to the
number of cycles required to complete the current instruction. Because the REV,
REVW and WAV instructions can take many cycles to complete, they are designed so
that they can be interrupted. Instruction execution resumes when interrupt execution
is complete. When the CPU begins to service an interrupt, the instruction queue is re-
filled, a return address is calculated, and then the return address and the contents of
the CPU registers are stacked as shown in
After the CCR is stacked, the I bit (and the X bit, if an XIRQ interrupt service request
caused the interrupt) is set to prevent other interrupts from disrupting the interrupt ser-
vice routine. Execution continues at the address pointed to by the vector for the high-
est-priority interrupt that was pending at the beginning of the interrupt sequence. At
the end of the interrupt service routine, an RTI instruction restores context from the
stacked registers, and normal program execution resumes.
MOTOROLA
7-4
Table
EXCEPTION PROCESSING
7-2.
REFERENCE MANUAL
CPU12
Advertisement
Table of Contents
