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EDIVS
Operation:
(Y : D)
Description:
Divides a signed 32-bit dividend by a 16-bit signed divisor, producing a
signed 16-bit quotient and a signed 16-bit remainder. All operands and
results are located in CPU registers. If an attempt to divide by zero is
made, the C status bit is set and the contents of double accumulator D
and index register Y do not change, but the states of the N and Z bits in
the CCR are undefined.
Condition Codes and Boolean Formulas:
S
–
N:
Z:
V:
C:
Addressing Modes, Machine Code, and Execution Times:
Source Form
EDIVS
CPU12
REFERENCE MANUAL
Extended Divide 32-Bit by 16-Bit
(Signed)
÷
(X) ⇒ Y; Remainder ⇒ D
X
H
I
N
Z
∆
∆
–
–
–
Set if MSB of result is set; cleared otherwise. Undefined after overflow or
division by zero.
Set if result is $0000; cleared otherwise. Undefined after overflow or division
by zero.
Set if the result was > $7FFF or < $8000; cleared otherwise. Undefined after
division by zero.
Set if divisor was $0000; cleared otherwise. (Indicates division by zero.)
Address Mode
INH
INSTRUCTION GLOSSARY
V
C
∆
∆
Object Code
18 14
EDIVS
Cycles
Access Detail
12
OffffffffffO
MOTOROLA
6-79
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