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B.7.7 Table Lookup and Interpolation
The CPU12 instruction set includes two instructions (TBL and ETBL) for lookup and
interpolation of compressed tables. Consecutive table values are assumed to be the x
coordinates of the endpoints of a line segment. The TBL instruction uses 8-bit table
entries (y-values) and returns an 8-bit result. The ETBL instruction uses 16-bit table
entries (y-values) and returns a 16-bit result.
An indexed addressing mode is used to identify the effective address of the data point
at the beginning of the line segment, and the data value for the end point of the line
segment is the next consecutive memory location (byte for TBL and word for ETBL).
In both cases, the B accumulator represents the ratio of (the x-distance from the be-
ginning of the line segment to the lookup point) to (the x-distance from the beginning
of the line segment to the end of the line segment). B is treated as an 8-bit binary
fraction with radix point left of the MSB, so each line segment is effectively divided
into 256 pieces. During execution of the TBL or ETBL instruction, the difference be-
tween the end point y-value and the beginning point y-value (a signed byte for TBL or
a signed word for ETBL) is multiplied by the B accumulator to get an intermediate
delta-y term. The result is the y-value of the beginning point, plus this signed interme-
diate delta-y value.
B.7.8 Extended Bit Manipulation
The M68HC11 CPU only allows direct or indexed addressing. This typically causes
the programmer to dedicate an index register to point at some memory area such as
the on-chip registers. The CPU12 allows all bit manipulation instructions to work with
direct, extended or indexed addressing modes.
B.7.9 Push and Pull D and CCR
The CPU12 includes instructions to push and pull the D accumulator and the CCR. It
is interesting to note that the order in which 8-bit accumulators A and B are stacked
for interrupts is the opposite of what would be expected for the upper and lower bytes
of the 16-bit D accumulator. The order used originated in the M6800, an 8-bit micro-
processor developed long before anyone thought 16-bit single-chip devices would be
made. The interrupt stacking order for accumulators A and B is retained for code
compatibility.
B.7.10 Compare SP
This instruction was added to the CPU12 instruction set to improve orthogonality and
high-level language support. One of the most important requirements for C high-level
language support is the ability to do arithmetic on the stack pointer for such things as
allocating local variable space on the stack. The LEAS –5,SP instruction is an exam-
ple of how the compiler could easily allocate five bytes on the stack for local variables.
LDX 5,SP+ loads X with the value on the bottom of the stack and deallocates five
bytes from the stack in a single operation that takes only two bytes of object code.
CPU12
REFERENCE MANUAL
M68HC11 TO M68HC12 UPGRADE PATH
MOTOROLA
B-15
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