Motorola HC12 Refrence Manual page 324

9.6.3 Cycle-by-Cycle Details for WAV and wavr
The WAV instruction is unusual in that the logic flow has two separate entry points.
The first entry point is the normal start of a WAV instruction. The second entry point is
used to resume the weighted average operation after a WAV instruction has been in-
terrupted. This recovery operation is called the wavr pseudo-instruction.
Figure 9-11 is a flow diagram of the WAV instruction including the wavr pseudo-in-
struction. Each rectangular box in this figure represents one CPU clock cycle. Decision
blocks and connecting arrows are considered to take no time at all. The letters in the
small rectangles in the upper left corner of the boxes correspond to execution cycle
codes (refer to SECTION 6 INSTRUCTION GLOSSARY
ters indicate a cycle where 8-bit or no data is transferred. Upper case letters indicate
cycles where 16-bit data could be transferred.
In terms of cycle-by-cycle bus activity, the $18 page select prebyte is treated as a spe-
cial 1-byte instruction. In cycle 1.0 of the WAV instruction, one word of program infor-
mation will be fetched into the instruction queue if the $18 is located at an odd address.
If the $18 is at an even address, the instruction queue cannot advance so there is no
bus access in this cycle.
There is no bus access in cycles 2.0 or 3.0. In cycle 3.0, three internal 16-bit temporary
registers are cleared in preparation for summation operations. The WAV instruction
maintains a 32-bit sum-of-products in TMP3 : TMP2 and a 16-bit sum-of-weights in
TMP1. By keeping these sums inside the CPU, bus accesses are reduced and the
WAV operation is optimized for high speed.
Cycles 4.0 through 11.0 form the eight cycle main loop for WAV. The value in the 8-bit
B accumulator is used to count the number of loop iterations. B is decremented at the
top of the loop in cycle 4.0, and the test for zero is located at the bottom of the loop
after cycle 11.0. Cycle 5.0 and 6.0 are used to fetch the 8-bit operands for one iteration
of the loop. X and Y index registers are used to access these operands. The index reg-
isters are incremented as the operands are fetched. Cycle 7.0 is used to accumulate
the current fuzzy output into TMP1. Cycles 8.0 through 10.0 are used to perform the
eight by eight multiply of F
TMP2 during cycles 10.0 and 11.0. Even though the sum-of-products will not exceed
24 bits, the sum is maintained in the 32-bit combined TMP3 : TMP2 register because
it is easier to use existing 16-bit operations than it would be to create a new smaller
operation to handle the high order bits of this sum.
Since the weighted average operation could be quite long, it is made to be interrupt-
ible. The usual longest latency path is from very early in cycle 7.0, through cycle 11.0,
to the top of the loop to cycle 4.0, through cycle 6.0 to the interrupt check. There is also
a three cycle (7.1 through 9.1) exit sequence making this latency path a total of 12 cy-
cles. There is an even longer path, but it is much less likely to occur. If an interrupt
comes near the beginning of cycle 2.1, when a weighted average operation is being
resumed after a previous interrupt, the latency path is 2.1 through 6.1 plus 7.0 through
11.0 plus 4.0 through 6.0 plus the exit 7.1 through 9.1. This is a worst-case total of 17
cycles.
MOTOROLA
9-24
times S . The multiply result is accumulated into TMP3 :
i i
FUZZY LOGIC SUPPORT
for details). Lower case let-
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