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When a value is read from memory, it cannot be used by the CPU until the second
cycle after the read takes place. This is due to access and propagation delays.
Since there is more than one flow path through the REV instruction, cycle numbers
have a decimal place. This decimal place indicates which of several possible paths is
being used. The CPU normally moves forward by one digit at a time within the same
flow (flow number is indicated after the decimal point in the cycle number). There are
two exceptions possible to this orderly sequence through an instruction. The first is a
branch back to an earlier cycle number to form a loop as in 6.0 to 4.0. The second type
of sequence change is from one flow to a parallel flow within the same instruction such
as 4.0 to 5.2, which occurs if the REV instruction senses an interrupt. In this second
type of sequence branch, the whole number advances by one and the flow number
changes to a new value (the digit after the decimal point).
In cycle 1.0, the CPU12 does an optional program word access to replace the $18 pre-
byte of the REV instruction. Notice that cycle 7.0 is also an O type cycle. One or the
other of these will be a program word fetch, while the other will be a free cycle where
the CPU does not access the bus. Although the $18 page prebyte is a required part of
the REV instruction, it is treated by the CPU12 as a somewhat separate single cycle
instruction.
Rule evaluation begins at cycle 2.0 with a byte read of the first element in the rule list.
Usually this would be the first antecedent of the first rule, but the REV instruction can
be interrupted, so this could be a read of any byte in the rule list. The X index register
is incremented so it points to the next element in the rule list. Cycle 3.0 is needed to
satisfy the required delay between a read and when data is valid to the CPU. Some
internal CPU housekeeping activity takes place during this cycle, but there is no bus
activity. By cycle 4.0, the rule element that was read in cycle 2.0 is available to the
CPU.
Cycle 4.0 is the first cycle of the main three cycle rule evaluation loop. Depending upon
whether rule antecedents or consequents are being processed, the loop will consist of
cycles 4.0, 5.0, 6.0, or the sequence 4.0, 5.0, 6.1. This loop is executed once for every
byte in the rule list, including the $FE separators and the $FF end-of-rules marker.
At each cycle 4.0, a fuzzy input or fuzzy output is read, except during the loop passes
associated with the $FE and $FF marker bytes, where no bus access takes place dur-
ing cycle 4.0. The read access uses the Y index register as the base address and the
previously read rule byte (R
value read here will be used during the next cycle 6.0 or 6.1. Besides being used as
the offset from Y for this read, the previously read R
rator character ($FE). If R
processing consequents of one rule to starting to process antecedents of the next rule.
At this transition, the A accumulator is initialized to $FF to prepare for the min opera-
tion to find the smallest fuzzy input. Also, if Rx is $FE, the V-bit is toggled to indicate
the change from antecedents to consequents, or consequents to antecedents.
During cycle 5.0, a new rule byte is read unless this is the last loop pass, and R
$FF (marking the end of the rule list). This new rule byte will not be used until cycle 4.0
of the next pass through the loop.
CPU12
REFERENCE MANUAL
) as an unsigned offset from Y. The fuzzy input or output
x
was $FE and the V-bit was one, this indicates a switch from
x
FUZZY LOGIC SUPPORT
is checked to see if it is a sepa-
x
is
x
MOTOROLA
9-17
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