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M68HC11
Equivalent
Mnemonic
CPU12 Instruction
ABX
LEAX B,X
ABY
LEAY B,Y
CLC
ANDCC #$FE
CLI
ANDCC #$EF
CLV
ANDCC #$FD
SEC
ORCC #$01
SEI
ORCC #$10
SEV
ORCC #$02
DES
LEAS –1,S
INS
LEAS 1,S
TAP
TFR A,CCR
TPA
TFR CCR,A
TSX
TFR S,X
TSY
TFR S,Y
TXS
TFR X,S
TYS
TFR Y,S
XGDX
EXG D,X
XGDY
EXG D,Y
All of the translations produce the same amount of or slightly more object code than
the original M68HC11 instructions. However, there are offsetting savings in other in-
structions. Y-indexed instructions in particular assemble into one byte less object
code than the same M68HC11 instruction.
The CPU12 has a two-page opcode map, rather than the four-page M68HC11 map.
This is largely due to redesign of the indexed addressing modes. Most of pages 2, 3,
and 4 of the M68HC11 opcode map are required because Y-indexed instructions use
different opcodes than X-indexed instructions. Approximately two-thirds of the
M68HC11 page 1 opcodes are unchanged in CPU12, and some M68HC11 opcodes
have been moved to page 1 of the CPU12 opcode map. Object code for each of the
moved instructions is one byte smaller than object code for the equivalent M68HC11
instruction.
Table B-2
on the CPU12.
Instruction set changes offset each other to a certain extent. Programming style also
affects the rate at which instructions appear. As a test, the BUFFALO monitor, an 8-
Kbyte M68HC11 assembly code program, was reassembled for the CPU12. The re-
sulting object code is six bytes smaller than the M68HC11 code. It is fair to conclude
that M68HC11 code can be reassembled with very little change in size.
MOTOROLA
B-2
Table B-1 Translated M68HC11 Mnemonics
Since CPU12 has accumulator offset indexing, ABX and ABY are
rarely used in new CPU12 programs. ABX was one byte on M68HC11
but ABY was two bytes. The LEA substitutes are two bytes.
ANDCC and ORCC now allow more control over the CCR, including
the ability to set or clear multiple bits in a single instruction. These
instructions took one byte each on M68HC11 while the ANDCC and
ORCC equivalents take two bytes each.
Unlike DEX and INX, DES and INS did not affect CCR bits in the
M68HC11, so the LEAS equivalents in CPU12 duplicate the function of
DES and INS. These instructions were one byte on M68HC11 and two
bytes on CPU12.
The M68HC11 had a small collection of specific transfer and exchange
instructions. CPU12 expanded this to allow transfer or exchange
between any two CPU registers. For all but TSY and TYS (which take
two bytes on either CPU), the CPU12 transfer/exchange costs one
extra byte compared to the M68HC11. The substitute instructions exe-
cute in one cycle rather than two.
shows instructions that assemble to one byte less object code
M68HC11 TO M68HC12 UPGRADE PATH
Comments
REFERENCE MANUAL
CPU12
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