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Table A-1 Instruction Set Summary (Continued)
Source
Form
see WAV
wavr
pseudo-
Resume executing an interrupted WAV in-
struction (recover intermediate results from
instruction
stack rather than initializing them to zero)
(D) ⇔ (X)
XGDX
Translates to EXG D, X
(D) ⇔ (Y)
XGDY
Translates to EXG D, Y
NOTES:
*Each cycle (~) is typically 125 ns for an 8-MHz bus (16-MHz oscillator).
**Refer to detailed instruction descriptions for additional information.
Key to
Table A-2
Addressing mode abbreviations:
DI — Direct
EX — Extended
ID — Indexed
IH — Inherent
IM — Immediate
RL — Relative
SP — Special
Cycle counts are for single-chip mode with 16-bit internal buses. Stack location (internal or external),
external bus width, and operand alignment can affect actual execution time.
CPU12
REFERENCE MANUAL
Operation
opcode (hex)
00
MNE
AA
addressing mode
INSTRUCTION REFERENCE
Addr.
Machine
Mode
Coding (hex)
Special
3C
INH
B7 C5
INH
B7 C6
cycle count
0
mnemonic
0
byte count
*
~
S X H I N Z V C
**
∆
–
–
? – ?
?
1
–
–
– – –
–
–
1
–
–
– – –
–
–
MOTOROLA
A-19
?
–
–
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