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7.4.4 External Interrupts
External interrupt service requests are made by asserting an active-low signal con-
nected to the IRQ pin. Typically, control bits in the device integration module affect
how the signal is detected and recognized.
The I bit serves as the IRQ interrupt enable flag. When an IRQ interrupt is recognized,
the I bit is set to inhibit interrupts during the interrupt service routine. Before other
maskable interrupt requests can be recognized, the I bit must be cleared. This is gen-
erally done by an RTI instruction at the end of the service routine.
7.4.5 Return from Interrupt Instruction (RTI)
RTI is used to terminate interrupt service routines. RTI is an 8-cycle instruction when
no other interrupt is pending, and a 10-cycle instruction when another interrupt is
pending. In either case, the first five cycles are used to restore (pull) the CCR, B:A, X,
Y, and the return address from the stack. If no other interrupt is pending at this point,
three program words are fetched to refill the instruction queue from the area of the re-
turn address and processing proceeds from there.
If another interrupt is pending after registers are restored, a new vector is fetched, and
the stack pointer is adjusted to point at the CCR value that was just recovered (SP =
SP – 9). This makes it appear that the registers have been stacked again. After the SP
is adjusted, three program words are fetched to refill the instruction queue, starting at
the address the vector points to. Processing then continues with execution of the in-
struction that is now at the head of the queue.
7.5 Unimplemented Opcode Trap
The CPU12 has opcodes in all 256 positions in the page 1 opcode map, but only 54
of the 256 positions on page 2 of the opcode map are used. If the CPU attempts to
execute one of the 202 unused opcodes on page 2, an unimplemented opcode trap
occurs. The 202 unimplemented opcodes are essentially interrupts that share a com-
mon interrupt vector, $FFF8:$FFF9.
The CPU12 uses the next address after an unimplemented page 2 opcode as a return
address. This differs from the M68HC11 illegal opcode interrupt, which uses the ad-
dress of an illegal opcode as the return address. In the CPU12, the stacked return ad-
dress can be used to calculate the address of the unimplemented opcode for software-
controlled traps.
CPU12
REFERENCE MANUAL
Table 7-2 Stacking Order on Entry to Interrupts
Memory Location
SP
SP +2
SP +4
SP +6
SP +8
EXCEPTION PROCESSING
CPU Registers
RTN
: RTN
H
L
Y
: Y
H
L
X
: X
H
L
B : A
CCR
MOTOROLA
7-5
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