Motorola HC12 Refrence Manual page 435

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SEI instruction 6-183
Set 1-3
Setting memory bits 6-48
SEV instruction 6-184
SEX instruction 5-2, 6-185
Shift instructions 5-8
Arithmetic 6-19 to 6-25
Logical 6-131 to 6-138
Sign extension instruction 6-185
Signed branches 5-13
Signed integers 2-5
Signed multiplication 5-7
Sign-extension instruction 5-2, C-1
Simple branches 5-13
Software interrupts 6-196, 7-1
Source code compatibility 1-1, B-1
Source form notation 6-3
Specific mnemonic 1-3
STAA instruction 6-186
STAB instruction 6-187
Stack 2-2, B-5 to B-6
Interrupts 6-177, 6-196
Stop and wait 6-189, 6-213
Subroutines 6-49, 6-52, 6-103, 6-176, 6-178
Traps 6-205
Stack operation instructions 5-20, 6-154 to 6-165
Stack pointer 2-1 to 2-2, 3-5, 6-49, 6-52, 6-66,
6-70 to 6-71, 6-75, 6-90, 6-92 to 6-93, 6-99,
6-103, 6-125, 6-128 to 6-130, 6-155 to 6-165,
6-178, 6-185, 6-190, 6-200 to 6-203,
6-209 to 6-212, C-1
Initialization 2-2
Manipulation 5-20, 6-66, 6-75, 6-99, 6-125,
6-128, 6-154 to 6-155, 6-190, 6-209 to 6-212
Stacking order 2-2, B-5
Stack pointer instructions 5-20, 6-66, 6-75, 6-99,
6-125, 6-128, 6-190, 6-203, 6-209 to 6-212,
B-15, C-1
Stack 16-bit data cycle 6-6
Stack 8-bit data cycle 6-6
Stacking instructions 6-154 to 6-155
Standard CPU12 address space 2-5
STD instruction 6-188
STOP instruction 2-3, 5-21, 6-189
Store instructions 5-1, 6-186 to 6-188,
6-190 to 6-192
STS instruction 6-190
STX instruction 6-191
STY instruction 6-192
SUBA instruction 6-193
SUBB instruction 6-194
SUBD instruction 6-195
Subroutine instructions 5-17
CPU12
REFERENCE MANUAL
Subroutines 4-3, 6-103, C-4 to C-5
Expanded memory 4-3, 5-17, 6-52, 6-176
Instructions 5-17, 6-49, 6-103, C-4 to C-5
Return 6-176, 6-178
Subtraction instructions 5-3, 6-179 to 6-181,
6-193 to 6-195
SWI instruction 5-18, 6-196, 7-6
Switch statements C-4
Symbols and notation 1-2
TAB instruction 6-197
Table interpolation instructions 5-12, 6-89, 6-201,
B-15
Tabular membership functions 9-26 to 9-27
TAP instruction 6-198
TBA instruction 6-199
TBEQ instruction 6-200, A-25
TBL instruction 5-12, 6-201, 9-1, 9-26 to 9-27
TBNE instruction 6-202, A-25
Termination of interrupt service routines 5-18,
6-177, 7-5
Termination of subroutines 6-176, 6-178
Test instructions 5-5, 6-35 to 6-36, 6-200, 6-202,
6-206 to 6-208
TFR instruction 6-185, 6-198, 6-203 to 6-204,
6-209 to 6-212
TPA instruction 6-204
Transfer and exchange instructions C-1
Transfer instructions 5-2, 6-197 to 6-199,
6-203 to 6-204, 6-209 to 6-212, B-11, B-13
Postbyte encoding A-24
TRAP instruction 5-18, 6-205, 7-5
TST 6-206
TST instruction 6-206
TSTA instruction 6-207
TSTB instruction 6-208
TSX instruction 6-209
TSY instruction 6-210
Twos-complement form 2-5
TXS instruction 6-211
Types of instructions
Addition and Subtraction 5-3
Background and null 5-22
Binary-coded decimal 5-4
Bit test and manipulation 5-7
Boolean logic 5-6
Branch 5-13
Clear, complement, and negate 5-6
Compare and test 5-5
Condition code 5-21
Decrement and increment 5-4
Fuzzy logic 5-9
T
MOTOROLA
I-7

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