Motorola HC12 Refrence Manual page 173

LBLS
If C + Z = 1, then (PC) + $0004 + Rel ⇒ PC
Operation:
For unsigned binary numbers, if (Accumulator)
Description: If LBLS is executed immediately after execution of CBA, CMPA, CMPB,
CMPD, CPX, CPY, SBA, SUBA, SUBB, or SUBD, a branch occurs if and
only if the unsigned binary number in the accumulator was less than or
equal to the unsigned binary number in memory. This instruction is gen-
erally not useful after INC/DEC, LD/ST, TST/CLR/COM because these
instructions do not affect the C status bit.
See
Condition Codes and Boolean Formulas:
S
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
LBLS rel16
Notes:
1. OPPP/OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and
three cycles if the branch is not taken.
Branch
Test Mnemonic
r>m LBGT
r≥m LBGE
r=m LBEQ
r≤m LBLE
r<m LBLT
r>m LBHI
r≥m LBHS/LBCC
r=m LBEQ
r≤m LBLS
r<m LBLO/LBCS
Carry LBCS
Negative LBMI
Overflow LBVS
r=0 LBEQ
Always LBRA
CPU12
REFERENCE MANUAL
Long Branch if Lower or Same
3.7 Relative Addressing Mode
X H I N Z
– – – – –
Address Mode
REL
Opcode Boolean
⊕
Z + (N
18 2E V) = 0
⊕
18 2C N V = 0
18 27 Z = 1
⊕
Z + (N
18 2F V) = 1
⊕
18 2D N V = 1
C + Z = 0
18 22
18 24 C = 0
18 27 Z = 1
C + Z = 1
18 23
18 25 C = 1
18 25 C = 1
18 2B N = 1
18 29 V = 1
18 27 Z = 1
18 20 —
INSTRUCTION GLOSSARY
for details of branch execution.
V C
– –
Object Code
18 23 qq rr
Complementary Branch
Test Mnemonic
r≤m LBLE
r<m LBLT
r≠m LBNE
r>m LBGT
r≥m LBGE
r≤m LBLS
r<m LBLO/LBCS
r≠m LBNE
r>m LBHI
r≥m LBHS/LBCC
No Carry LBCC
Plus LBPL
No Overflow LBVC
r≠0 LBNE
Never LBRN
LBLS
≤
(Memory), then branch
Cycles Access Detail
1
4/3
OPPP/OPO
Opcode Comment
18 2F Signed
18 2D Signed
18 26 Signed
18 2E Signed
18 2C Signed
18 23 Unsigned
18 25 Unsigned
18 26 Unsigned
18 22 Unsigned
18 24 Unsigned
18 24 Simple
18 2A Simple
18 28 Simple
18 26 Simple
18 21 Unconditional
MOTOROLA
6-113