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vance after the odd byte executes, or the first byte of the next instruction would be
lost. In this case, the O cycle appears as a free cycle since the queue is not ready to
accept the next word of program information. If this same instruction had been mis-
aligned, the queue would be ready to advance and the O cycle would be used to per-
form a program word fetch.
In a single-chip system or in a system with the program in 16-bit memory, both the
free cycle and the program fetch cycle take one bus cycle. In a system with the pro-
gram in an external 8-bit memory, the O cycle takes one bus cycle when it appears as
a free cycle, but it takes two bus cycles when used to perform a program fetch. In this
case, the on-chip integration module freezes the CPU clocks long enough to perform
the cycle as two smaller accesses. The CPU handles only 16-bit data, and is not
aware that the 16-bit program access is split into two 8-bit accesses.
In order to allow development systems to track events in the CPU12 instruction
queue, two status signals (IPIPE[1:0]) provide information about data movement in
the queue and about the start of instruction execution. A development system can
use this information along with address and data information to externally reconstruct
the queue. This representation of the queue can also track both the data and address
buses.
B.4.3 Stack Function
Both the M68HC11 and the CPU12 stack nine bytes for interrupts. Since this is an
odd number of bytes, there is no practical way to assure that the stack will stay
aligned. To assure that instructions take a fixed number of cycles regardless of stack
alignment, the internal RAM in M68HC12 MCUs is designed to allow single cycle 16-
bit accesses to misaligned addresses. As long as the stack is located in this special
RAM, stacking and unstacking operations take the same amount of execution time,
regardless of stack alignment. If the stack is located in an external 16-bit RAM, a
PSHX instruction can take two or three cycles depending upon the alignment of the
stack. This extra access time is transparent to the CPU because the integration mod-
ule freezes the CPU clocks while it performs the extra 8-bit bus cycle required for a
misaligned stack operation.
The CPU12 has a "last-used" stack rather than a "next-available" stack like the
M68HC11 CPU. That is, the stack pointer points to the last 16-bit stack address used,
rather than to the address of the next available stack location. This generally has very
little effect, because it is very unusual to access stacked information using absolute
addressing. The change allows a 16-bit word of data to be removed from the stack
without changing the value of the SP twice.
To illustrate, consider the operation of a PULX instruction. With the next-available
M68HC11 stack, if the SP = $01F0 when execution begins, the sequence of opera-
tions is: SP = SP + 1; load X from $01F1:01F2; SP = SP + 1; and the SP ends up at
$01F2. With the last-used CPU12 stack, if the SP = $01F0 when execution begins,
the sequence is: load X from $01F0:01F1; SP = SP + 2; and the SP again ends up at
$01F2. The second sequence requires one less stack pointer adjustment.
CPU12
REFERENCE MANUAL
M68HC11 TO M68HC12 UPGRADE PATH
MOTOROLA
B-5
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