Motorola HC12 Refrence Manual page 348

Table A-1 Instruction Set Summary (Continued)
Source
Form
LBRN rel
Long Branch Never (if 1 = 0)
LBVC rel Long Branch if Overflow Bit Clear (if V=0)
LBVS rel Long Branch if Overflow Bit Set (if V = 1)
(M) ⇒ A
LDAA opr
Load Accumulator A
(M) ⇒ B
LDAB opr
Load Accumulator B
(M:M+1) ⇒ A:B
LDD opr
Load Double Accumulator D (A:B)
(M:M+1) ⇒ SP
LDS opr
Load Stack Pointer
(M:M+1) ⇒ X
LDX opr
Load Index Register X
(M:M+1) ⇒ Y
LDY opr
Load Index Register Y
Effective Address ⇒ SP
LEAS opr
Load Effective Address into SP
MOTOROLA
A-10
Operation
INSTRUCTION REFERENCE
Addr. Machine
Mode Coding (hex)
REL 18 21 qq rr
REL 18 28 qq rr 4/3
REL 18 29 qq rr 4/3
IMM 86 ii
DIR 96 dd
EXT B6 hh ll
IDX A6 xb
IDX1 A6 xb ff
IDX2 A6 xb ee ff
[D,IDX] A6 xb
[IDX2] A6 xb ee ff
IMM C6 ii
DIR D6 dd
EXT F6 hh ll
IDX E6 xb
IDX1 E6 xb ff
IDX2 E6 xb ee ff
[D,IDX] E6 xb
[IDX2] E6 xb ee ff
IMM CC jj kk
DIR DC dd
EXT FC hh ll
IDX EC xb
IDX1 EC xb ff
IDX2 EC xb ee ff
[D,IDX] EC xb
[IDX2] EC xb ee ff
IMM CF jj kk
DIR DF dd
EXT FF hh ll
IDX EF xb
IDX1 EF xb ff
IDX2 EF xb ee ff
[D,IDX] EF xb
[IDX2] EF xb ee ff
IMM CE jj kk
DIR DE dd
EXT FE hh ll
IDX EE xb
IDX1 EE xb ff
IDX2 EE xb ee ff
[D,IDX] EE xb
[IDX2] EE xb ee ff
IMM CD jj kk
DIR DD dd
EXT FD hh ll
IDX ED xb
IDX1 ED xb ff
IDX2 ED xb ee ff
[D,IDX] ED xb
[IDX2] ED xb ee ff
IDX 1B xb
IDX1 1B xb ff
IDX2 1B xb ee ff
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S X H I N Z V C
3 – – – – – – –
– – – – – – –
– – – – – – –
– – ∆ ∆
1 – – 0
3
3
3
3
4
6
6
– – ∆ ∆
1 – – 0
3
3
3
3
4
6
6
– – ∆ ∆
2 – – 0
3
3
3
3
4
6
6
– – ∆ ∆
2 – – 0
3
3
3
3
4
6
6
– – ∆ ∆
2 – – 0
3
3
3
3
4
6
6
– – ∆ ∆
2 – – 0
3
3
3
3
4
6
6
2 – – – – – – –
2
2
CPU12
REFERENCE MANUAL
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