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Each window has an associated page select register that selects external memory
pages to be accessed via the window. Only one page at a time can occupy a window;
the value in the register must be changed to access a different page of memory. With
8-bit registers, there can be up to 256 expansion pages per window, each page the
same size as the window.
For data and extra windows, page switching is accomplished by means of normal read
and write instructions. This is the traditional method of managing a bank-switching
system. The CPU12 CALL and RTC instructions automatically manipulate the pro-
gram page select (PPAGE) register for the program window.
In M68HC12 expanded memory systems, control registers, vector spaces, and a por-
tion of on-chip memory are located in unpaged portions of the 64-Kbyte address
space. The stack and I/O addresses should also be placed in unpaged memory to
make them accessible from any overlay page.
The initial portions of exception handlers must be located in unpaged memory be-
cause the 16-bit exception vectors cannot point to addresses in paged memory. How-
ever, service routines can call other routines in paged memory. The upper 16-Kbyte
block of memory space ($C000–$FFFF) is unpaged. It is recommended that all reset
and interrupt vectors point to locations in this area.
Although internal MCU resources, such as control registers and on-chip memory, have
default addresses out of reset, each can typically be relocated by changing the default
values in control registers. Normally, I/O addresses, control registers, vector spaces,
overlay windows, and on-chip memory are not mapped so that their respective ad-
dress ranges overlap. However, there is an access priority order that prevents access
conflicts should such overlaps occur.
sources with higher precedence block access to those with a lower precedence. The
windows have lowest priority — registers, exception vectors, and on-chip memory are
always visible to a program regardless of the values in the page select registers.
When background debugging is enabled and active, the CPU executes code located
in a small on-chip ROM mapped to addresses $FF20 to $FFFF, and BDM control reg-
isters are accessible at addresses $FF00 to $FF06. The BDM ROM replaces the reg-
ular system vectors while BDM is active, but BDM resources are not in the memory
map during normal execution of application programs.
MOTOROLA
10-2
Table 10-1
Table 10-1 Mapping Precedence
Precedence
1
2
Exception Vectors/BDM ROM
3
4
5
6
MEMORY EXPANSION
shows the mapping precedence. Re-
Resource
Registers
RAM
EEPROM
Flash
Expansion Windows
CPU12
REFERENCE MANUAL
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