B.5 Improved Indexing - Motorola HC12 Refrence Manual

The stack pointer change also affects operation of the TSX and TXS instructions. In
the M68HC11, TSX increments the SP by one during the transfer. This adjustment
causes the X index to point to the last stack location used. The TXS instruction oper-
ates similarly, except that it decrements the SP by one during the transfer. CPU12
TSX and TXS instructions are ordinary transfers — the CPU12 stack requires no ad-
justment.
For ordinary use of the stack, such as pushes, pulls, and even manipulations involv-
ing TSX and TXS, there are no differences in the way the M68HC11 and the CPU12
stacks look to a programmer. However, the stack change can affect a program algo-
rithm in two subtle ways.
The LDS #$xxxx instruction is normally used to initialize the stack pointer at the start
of a program. In the M68HC11, the address specified in the LDS instruction is the first
stack location used. In the CPU12, however, the first stack location used is one ad-
dress lower than the address specified in the LDS instruction. Since the stack builds
downward, M68HC11 programs reassembled for the CPU12 operate normally, but
the program stack is one physical address lower in memory.
In very uncommon situations, such as test programs used to verify CPU operation, a
program could initialize the SP, stack data, and then read the stack via an extended
mode read (it is normally improper to read stack data from an absolute extended ad-
dress). To make an M68HC11 source program that contains such a sequence work
on the CPU12, change either the initial LDS #$xxxx, or the absolute extended ad-
dress used to read the stack.

B.5 Improved Indexing

The CPU12 has significantly improved indexed addressing capability, yet retains
compatibility with the M68HC11. The one cycle and one byte cost of doing Y-related
indexing in the M68HC11 has been eliminated. In addition, high level language re-
quirements, including stack relative indexing and the ability to perform pointer arith-
metic directly in the index registers, have been accommodated.
The M68HC11 has one variation of indexed addressing that works from X or Y as the
reference pointer. For X indexed addressing, an 8-bit unsigned offset in the instruc-
tion is added to the index pointer to arrive at the address of the operand for the in-
struction. A load accumulator instruction assembles into two bytes of object code, the
opcode and a 1-byte offset. Using Y as the reference, the same instruction assem-
bles into three bytes (a page prebyte, the opcode, and a one-byte offset.) Analysis of
M68HC11 source code indicates that the offset is most frequently zero and very sel-
dom greater than four.
The CPU12 indexed addressing scheme uses a postbyte plus 0, 1, or 2 extension
bytes after the instruction opcode. These bytes specify which index register is used,
determine whether an accumulator is used as the offset, implement automatic pre/
post increment/decrement of indices, and allow a choice of 5-, 9-, or 16-bit signed off-
sets. This approach eliminates the differences between X and Y register use and dra-
matically enhances indexed addressing capabilities.
MOTOROLA
B-6
M68HC11 TO M68HC12 UPGRADE PATH CPU12
REFERENCE MANUAL