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5.1.6 Addressing Modes
Addressing in the CPU32 is register oriented. Most instructions allow the results of the
specified operation to be placed either in a register or directly in memory; this flexibility
eliminates the need for extra instructions to store register contents in memory.
The seven basic addressing modes are as follows:
• Register Direct
• Register Indirect
• Register Indirect with Index
• Program Counter Indirect with Displacement
• Program Counter Indirect with Index
• Absolute
• Immediate
Included in the register indirect addressing modes are the capabilities to postincrement,
predecrement, and offset. The PC relative mode also has index and offset capabilities. In
addition to these addressing modes, many instructions implicitly specify the use of the SR,
SP and/or PC. Addressing is explained fully in the M68000PM/AD, M68000 Family
Programmer's Reference Manual .
5.1.7 Instruction Set
The instruction set of the CPU32 is very similar to that of the MC68020 (see Table 5-1).
Two new instructions have been added to facilitate embedded control applications:
LPSTOP and table lookup and interpolate (TBL). The following M68020 instructions are
not implemented on the CPU32:
BFxxx
— Bit Field Instructions (BFCHG, BFCLR, BFEXTS, BFEXTU,
CALLM, RTM — Call Module, Return Module
CAS, CAS2
— Compare and Set (Read-Modify-Write Instructions)
cpxxx
— Coprocessor Instructions (cpBcc, cpDBcc, cpGEN, cpRESTORE,
PACK, UNPK — Pack, Unpack BCD Instructions
The CPU32 traps on unimplemented instructions or illegal effective addressing modes,
allowing user-supplied code to emulate unimplemented capabilities or to define special-
purpose functions. However, Motorola reserves the right to use all currently
unimplemented instruction operation codes for future M68000 core enhancements.
MOTOROLA
Freescale Semiconductor, Inc.
BFFFO, BFINS, BFSET, BFTST)
cpSAVE, cpScc, cpTRAPcc)
MC68340 USER'S MANUAL
For More Information On This Product,
Go to: www.freescale.com
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