Xilinx Virtex-4 User Manual page 94

Chapter 3: Client, Host, and MDIO Interfaces
Write Transaction
Figure 3-47
addressed MMD (PHYAD) device takes the 16-bit word in the Data field and writes it to
the register at REGAD.
MDC
MDIO
Z Z 1 1 1 0 1
IDLE 32 bits ST
PRE
Read Transaction
Figure 3-48
(PHYAD) device returns the 16-bit word from the register at REGAD.
MDC
MDIO
Z Z 1 1 1 0 1
IDLE 32 bits ST
PRE
The IEEE specification 802.3-2002 provides details of the register map of MMD (PHY layer
devices) and a fuller description of the operation of the MDIO interface.
Special Note on the Physical Addresses
The PHYAD field for the MDIO frame is defined in IEEE Std 802.3, Clause 22.2.4.5.5. This
address field is a 5-bit binary value capable of addressing 32 unique addresses. However,
every MMD must respond to address 0. Therefore, this address location can be used to
write a single command that is obeyed by all attached MMDs such as a reset or power-
down command.
This requirement dictates that the PHYAD for any particular MMD must not be set to 0 to
avoid possible MDIO contention.
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94
shows a Write transaction across the MDIO, as defined by OP = 0b01. The
STA drives MDIO
0 1 P4 P3 P2 P1 P0 R4 R3 R2 R1 R0 1 0 D15
OP PHYAD REGAD
Figure 3-47: MDIO Write Transaction
shows a Read transaction as defined by OP = 0b10. The addressed MMD
STA drives MDIO
1 0 P4 P3 P2 P1 P0 R4 R3 R2 R1 R0 Z 0 D15
OP PHYAD REGAD
Figure 3-48: MDIO Read Transaction
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D13 D11 D9 D7
D14 D12 D10 D8
TA 16-bit WRITE DATA
MMD drives MDIO
D13 D11 D9 D7
D14 D12 D10 D8
TA 16-bit READ DATA
Embedded Tri-Mode Ethernet MAC User Guide
D5 D3 D1 Z Z
D6 D4 D2 D0
IDLE
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D5 D3 D1 Z Z
D6 D4 D2 D0
IDLE
UG074_3_73_103106
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