Xilinx Virtex-4 User Manual page 168

Fpga embedded tri-mode ethernet mac
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Chapter 7: Using the Embedded Ethernet MAC
DCM reset module is provided to generate the required reset pulse and users need to
connect the output of this module to the DCM reset pins. This can be achieved by
connecting the reset_200ms_# signal to the reset_200ms_in_# signal at any level of example
design HDL hierarchy. See the block level wrapper file for more information.
For further details on the Ethernet MAC wrappers, refer to DS307, Virtex-4 Embedded Tri-
Mode Ethernet MAC Wrapper Data Sheet and GSG240, Virtex-4 Embedded Tri-Mode Ethernet
MAC Wrapper Getting Started Guide.
www.BDTIC.com/XILINX
168
www.xilinx.com
Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
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