Xilinx Virtex-4 User Manual page 11

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Interfacing to an FPGA Fabric-Based Statistics Block
When the Ethernet MAC Is Implemented with the Host Bus . . . . . . . . . . . . . . . . . . . 161
When the Ethernet MAC Is Implemented with the DCR Bus . . . . . . . . . . . . . . . . . . . 163
Chapter 7: Using the Embedded Ethernet MAC
Accessing the Ethernet MAC from the CORE Generator tool
Simulating the Ethernet MAC using the Ethernet MAC wrappers
Appendix A: Ethernet MAC Timing Model
Timing Parameters
Input Setup/Hold Times Relative to Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Clock to Output Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Core Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Timing Diagram and Timing Parameter Tables
www.BDTIC.com/XILINX
Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
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www.xilinx.com
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