Table of Contents
Advertisement
Chapter 3: Client, Host, and MDIO Interfaces
Table 3-30: Detailed Address Codes for DCR Host Bus Access (Cont'd)
Address
Codes
E0_GENERALCONFIG
0x390
0x394:0x39F
IRSTATUS
0x3A0
IRENABLE
0x3A4
0x3A8:0x3AF
MIIMWRDATA
0x3B0
MIIMCNTL
0x3B4
0x3B8:0x5FF
EMAC1 Registers
E1_RXCONFIGW0
0x600
E1_RXCONFIGW1
0x640
E1_TXCONFIG
0x680
E1_FLOWCONTROL
0x6C0
E1_EMACCONFIG
0x700
E1_RGMII_SGMII
0x720
E1_MGMTCONFIG
0x740
E1_UNICASTADDRW0
0x780
E1_UNICASTADDRW1
0x784
E1_ADDRTABLECONFIGW0
0x788
E1_ADDRTABLECONFIGW1
0x78C
E1_GENERALCONFIG
0x790
IRSTATUS
0x7A0
IRENABLE
0x7A4
0x7A8:0x7AF
MIIMWRDATA
0x7B0
MIIMCNTL
0x7B4
0x7B8:0x7FF
www.BDTIC.com/XILINX
92
Register Names
www.xilinx.com
Description
Promiscuous mode, 0x00000000 bits
[31:0].
Reserved.
Access done, interrupt request status.
Interrupt request enable.
Reserved.
MDIO write data.
Decode address for MDIO
address output.
Reserved.
Receiver configuration word 0.
Receiver configuration word 1.
Transmitter configuration.
Flow control configuration.
Ethernet MAC configuration.
RGMII/SGMII configuration.
Management configuration.
Unicast address [31:0].
0x0000, Unicast Address [47:32].
Multicast address data[31:0]
0x00, RNW,
00000, ADDR[1:0],
Multicast address data[47:32].
Promiscuous mode, 0x00000000 bits
[31:0].
Access done, interrupt request status.
Interrupt request enable.
Reserved.
MDIO write data.
Decode address for MDIO
address output.
Reserved.
Embedded Tri-Mode Ethernet MAC User Guide
Ethernet MAC
R/W
Register Address
R/W
0x390
-
R/W
0x3A0
R/W
0x3A4
R/W
0x3B0
W
0x3B4
-
R/W
0x600
R/W
0x640
R/W
0x680
R/W
0x6C0
R/W
0x700
0x720
R/W
0x740
R/W
0x780
R/W
0x784
R/W
0x788
R/W
0x78C
R/W
0x790
R/W
0x7A0
R/W
0x7A4
R/W
0x7B0
W
0x7B4
-
UG074 (v2.2) February 22, 2010
R
-
-
R
-
Advertisement
Table of Contents
