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R
Table 3-24: DCR Control Register cntlReg
DCR
Offset
0
1
2
3
4
0xE
Bit
[0:15]
Reserved.
Write Enable – When this bit is asserted, the data in either dataRegLSW or dataRegMSW is
[16]
written into an Ethernet MAC register. When this bit is deasserted, the operation to be
performed is read.
[17:20]
Reserved.
EMAC1SEL – When this bit is asserted, the address code is for the EMAC1 registers.
[21]
Otherwise, the address code is for the EMAC0 registers. This bit is essentially the bit [10] of
the address code.
Address Code – the DCR bus bridge translates this address code into the Ethernet MAC
[22:31]
register address. See
www.BDTIC.com/XILINX
Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
RESERVED
Description
Table 3-30, page 91
for address code.
www.xilinx.com
RESERVED
ADDRESS_CODE
Host Interface
Default Value
All 0s
0
All 0s
0
All 0s
85
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