Xilinx Virtex-4 User Manual page 164

Chapter 6: Use Models
EMAC I/O Pin
host_clk
HOSTMIIMRDY
HOSTRDDATA[15]
HOSTRDDATA[8:0]
HOSTRDDATA[9]
HOSTRDDATA[10]
HOSTWRDATA[31:0]
Figure 6-3
Statistics block, where the LogiCORE Ethernet statistics counters are accessed via the DCR
bus. DS323, LogiCORE Ethernet Statistics Data Sheet, provides a a full description of the
Ethernet Statistics LogiCORE block.
Ethernet Statistics blocks to both Ethernet MACs within the Ethernet MAC block. If
statistics are required for only one Ethernet MAC, then the multiplexing between the
statistics cores is simply replaced with a straight-through connection.
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164
6 Clocks
Figure 6-2: Statistics Register Read Timing
shows how to integrate the Ethernet MAC with the LogiCORE Ethernet
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LSW MSW
Figure 6-3 illustrates how to connect LogiCORE
Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
R
Equivalent standalone
host bus signal
HOSTMIIMSEL
HOSTREQ
HOSTADDR[8:0]
HOSTADDR[9]
HOSTEMAC1SEL
HOSTRDDATA[31:0]
UG074_4_02_112705