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R
Table 3-14: Management Configuration Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
0x340
Bit
Clock divide [5:0]: This value is used to derive the
[5:0]
EMAC#PHYMCLKOUT for external devices.
See
"MDIO Interface," page
MDIO enable: When this bit is 1, the MDIO interface is used to
access the PHY. When this bit is 0, the MDIO interface is
[6]
disabled, and the MDIO signals remain inactive.
See
"MDIO Interface," page
[31:7]
Reserved.
Figure 3-40
management interface. When accessing the configuration registers (i.e., when
HOSTADDR[9] = 1 and HOSTMIIMSEL = 0), the upper bit of HOSTOPCODE functions as
an active Low write-enable signal. The lower HOSTOPCODE bit (bit[0]) is a "don't care."
www.BDTIC.com/XILINX
Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
RESERVED
Description
93.
93.
shows the write timing for the configuration registers through the
HOSTCLK
HOSTMIIMSEL
HOSTOPCODE[1]
HOSTADDR[8:0]
HOSTADDR[9]
HOSTWRDATA[31:0]
Figure 3-40: Configuration Register Write Timing
www.xilinx.com
Host Interface
9
8
7
6
5
4
CLOCK_DIVIDE[5:0]
Default Value
All 0s
TIEEMAC#CONFIGVEC[73]
–
ug074_3_42_080805
3
2
1
0
R/W
R/W
R/W
79
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