Xilinx Virtex-4 User Manual page 18

Chapter 2: Ethernet MAC Architecture
A detailed block diagram of the 10/100/1000 Ethernet MAC is shown in
physical side, it consists of the GMII and RGMII interfaces using standard I/Os to access
data and control signals to an external physical interface. In addition, the PCS/PMA
sublayer interfaces directly to the MGT.
The client side consists of the user transmit and receive interfaces. The flow control module
keeps traffic from being congested in the Ethernet MAC. The Management Data I/O
interface, (MDIO), allows access to the control and status registers in the external physical
interface or in the PCS sublayer when configured in 1000BASE-X and SGMII modes.
The clock management module automatically configures the output clocks to the correct
frequency based on the internal speed of the Ethernet MAC (10 Mb/s, 100 Mb/s, or
1000 Mb/s) and the Ethernet MAC mode settings (GMII, MII, RGMII, SGMII, and
1000BASE-X).
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ClientTx1/Rx1
DCR Bus
To PowerPC 405 block
Generic Host Bus
ClientTx0/Rx0
Ethernet MAC
Block
FPGA Fabric
Figure 2-1: Ethernet MAC Block
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StatsIP1
Rx Stats MUX1 Tx Stats MUX1
EMAC1
DCR
Bridge
Host Interface
EMAC0
Rx Stats MUX0 Tx Stats MUX0
StatsIP0
Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
R
Tx1/Rx1
PHY
Tx0/Rx0
ug074_2_01_091704
Figure 2-2. On the