Xilinx Virtex-4 User Manual page 43

R
Back-to-Back Transfers
Back-to-back transfers can occur when the Ethernet MAC client is immediately ready to
transmit a second frame of data following completion of the first frame. In
end of the first frame is shown on the left. At the clock cycle immediately following the
final byte of the first frame, CLIENTEMAC#TXDVLD is deasserted by the client. One clock
cycle later, CLIENTEMAC#TXDVLD is asserted High. This indicates that the first byte of
the destination address of the second frame is awaiting transmission on
CLIENTEMAC#TXD.
CLIENTEMAC#TXCLIENTCLKIN
CLIENTEMAC#TXDVLD
EMAC#CLIENTTXACK
CLIENTEMAC#TXFIRSTBYTE
CLIENTEMAC#TXUNDERRUN
EMAC#CLIENTTXCOLLISION
EMAC#CLIENTTXRETRANSMIT
CLIENTEMAC#TXD[7:0]
EMAC#PHYTXD[7:0]
(SGMII or 1000BASE-X
PCS/PMA only)
EMAC#PHYTXCHARISK
(SGMII or 1000BASE-X
PCS/PMA only)
EMAC#PHYCHARDISPMODE
(SGMII or 1000BASE-X
PCS/PMA only)
When the Ethernet MAC is ready to accept data, EMAC#CLIENTTXACK is asserted and
the transmission continues in the same manner as the single frame case. The Ethernet MAC
defers the assertion of EMAC#CLIENTTXACK to comply with inter-packet gap
requirements and flow control requests.
www.BDTIC.com/XILINX
Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
Figure 3-6: Back-to-Back Frame Transmission
www.xilinx.com
DA
FCS
/T/ /R/ /I1/ /I2/ /I2/
Client Interface
Figure 3-6, the
SA
/I2/ /I2/ /S/
ug074_3_08_063005
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